Khanh Thai
Grumman Aircraft Corporation
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Publication
Featured researches published by Khanh Thai.
compound semiconductor integrated circuit symposium | 2010
Augusto Gutierrez-Aitken; Patty Chang-Chien; D. Scott; Kelly Hennig; E. Kaneshiro; Peter Nam; Neir Cohen; Daniel Ching; Khanh Thai; Bert Oyama; Joe Zhou; Craig Geiger; Ben Poust; Matthew Parlee; Randy Sandhu; Wen Phan; Aaron Oki; Reynold Kagiwada
Northrop Grumman Aerospace Systems (NGAS) is developing an Advanced Heterogeneous Integration (AHI) process to integrate III-V semiconductor chiplets on CMOS wafers under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program. The objective of the program is to have a heterogeneous interconnect pitch and length less than 5 um to enable intimate transistor scale integration. This integration will enable significant improvement in dynamic range and bandwidth of high performance mixed signal circuits.
international microwave symposium | 2009
Augusto Gutierrez-Aitken; Patty Chang-Chien; Wen Phan; D. Scott; Bert Oyama; Randy Sandhu; Joe Zhou; Peter Nam; Kelly Hennig; Matthew Parlee; Ben Poust; Khanh Thai; Craig Geiger; Aaron Oki; Reynold Kagiwada
Northrop Grumman Space Technology (NGST) is developing an Advanced Heterogeneous Integration (AHI) process to integrate III-V semiconductor chiplets on CMOS wafers under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program. The objective of the program is to have a heterogeneous interconnect pitch and length less than 5 um to enable intimate transistor scale integration. This integration will enable significant improvement in ADC dynamic range and bandwidth
radio frequency integrated circuits symposium | 2014
Tim LaRocca; Yi-Cheng Wu; Khanh Thai; Rob Snyder; Naveen Daftari; Owen Fordham; Paul Rodgers; Monte Watanabe; Yeat Yang; Mohammad Ardakani; Waleed Namoos; Sumiko Poust; Mau-Chung Frank Chang
A 94GHz 64QAM 1Gbps reconfigurable system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) and back-etched thru silicon waveguide power combiners is presented. The SoC includes a 7M gate ASIC with reconfigurable digital modulation and transmit pre-coding. The ASIC feeds two 10b 1.4GHz current-steering DACs followed by a direct conversion IQ modulator driving eight DAPAs. A 64QAM signal achieves 3.9% EVM with 50dBc ACPR at 94GHz. The data rate is 1.05Gbps and the output power exceeds 10dBm. DC power is 2.1W. The SoC uses IBM 12SOI CMOS.
compound semiconductor integrated circuit symposium | 2014
Augusto Gutierrez-Aitken; Kelly Hennig; D. Scott; Ken Sato; Wesley Chan; Benjamin Poust; Xiang Zeng; Khanh Thai; Eric Nakamura; E. Kaneshiro; Nancy Lin; Cedric Monier; Ioulia Smorchkova; Bert Oyama; Aaron Oki; Reynold Kagiwada; Greg Chao
Northrop Grumman Aerospace Systems (NGAS) under the Diverse Accessible Heterojunction Integration (DAHI) DARPA program is developing heterogeneous integration processes, process design kit (PDK) and thermal analysis tools to integrate deep submicron CMOS, Indium Phosphide (InP) heterojunction bipolar transistors (HBTs), Gallium Nitride (GaN) high electron mobility transistors (HEMTs) and high-Q passive technologies for advanced DoD and other government systems.
radio frequency integrated circuits symposium | 2013
Tim LaRocca; Yi-Cheng Wu; Rob Snyder; Jasmine Patel; Khanh Thai; Colin Wong; Yeat Yang; Leland Gilreath; Monte Watanabe; Hao Wu; Mau-Chung Frank Chang
A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter drives eight parallel combined DAPAs. The chip is packaged in aluminum housing with WR22 outputs. A 64QAM signal achieves 1.8% EVM with 33dBc ACPR at 45GHz. The data rate is 450Mbps and the integrated output power exceeds -10dBm.
IEEE Journal of Solid-state Circuits | 2013
Bert Oyama; Daniel Ching; Khanh Thai; Augusto Gutierrez-Aitken; Vipul J. Patel
Gigahertz-rate Digital-to-Analog Converters (DACs) have become readily available from several commercial vendors but have been unable to achieve >;70 dB spurious-free dynamic range (SFDR) performance over a wide bandwidth (≥500MHz). This paper presents the results of a unique, heterogeneously-integrated (InP HBT with 0.18um silicon CMOS), 13-bit 1.33Gsps DAC that achieves >;70dB SFDR across a 500MHz bandwidth in the second Nyquist zone (750MHz to 1250MHz).
compound semiconductor integrated circuit symposium | 2012
Bert Oyama; Daniel Ching; Khanh Thai; Augusto Gutierrez-Aitken; N. Cohen; D. Scott; Kelly Hennig; E. Kaneshiro; Peter Nam; J. Chen; Patty Chang-Chien; Vipul J. Patel
Abstract - Gigahertz-rate Digital-to-Analog Converters (DACs) have become readily available from several commercial vendors but have been unable to achieve >70 dB spurious-free dynamic range (SFDR) performance over a wide bandwidth (≥500MHz). This paper presents the results of a unique, heterogeneously-integrated (InP HBT with 0.18um silicon CMOS), 13-bit 1.33Gsps DAC that achieves >70dB SFDR across a 500MHz bandwidth in the second Nyquist zone (750MHz to 1250MHz).
Meeting Abstracts | 2008
Patty Chang-Chien; Augusto Gutierrez-Aitken; Rajinder Sandhu; Kelly Hennig; D. Scott; Joe Zhou; Peter Nam; Craig Geiger; Ben Poust; Mattew Parlee; Khanh Thai; Wen Phan; Bert Oyama
Northrop Grumman Space Technology has developed an integration technology that is capable of intimately integrating III-V semiconductor devices with Si CMOS under DARPA’s COSMOS program. The integration approach is based on a direct face-to-face bonding between pre-fabricated III-V chiplets and CMOS wafers. It is capable of integrating CS (compound semiconductor) devices from smaller wafer substrates to a larger Si host wafer as well as integrating multiple CS technologies onto the same Si CMOS host wafer. This process can be applied to virtually any CS and Si technologies. Figure 1(a) shows the main steps of the AHI (Advanced Heterogeneous Integration) approach: Chiplet singulation, chiplet transfer and chiplet bonding. Figure 1(b) is the simplified flow diagram of the AHI process. Figure 2(a) is a cross-sectional presentation of an integrated CS/CMOS circuit and Figure 2(b) is a SEM photograph of the fabricated circuit, showing the InP chiplet on a silicon substrate. Integrated differential amplifiers (DAs) have been demonstrated using this 3D AHI integration approach. Figure 3 presents the data obtained from one of the integrated DAs. This DA demonstration integrates the 0.18um Silicon CMOS technology with 6 layers of interconnections from Jazz Semiconductor and NGST’s 0.4um emitter high speed HBT technology. Further integration details on AHI as well as demonstrated integrated circuit data will be presented in the full paper.
IEEE Microwave Magazine | 2017
Augusto Gutierrez-Aitken; Bryan Wu; D. Scott; Ken Sato; Benjamin Poust; Monte Watanabe; Cedric Monier; Nancy Lin; Xiang Zeng; Eric Nakamura; Peter Cheng; Eric Kaneshiro; Wesley Chan; Ioulia Smorchkova; Khanh Thai; Sujane Wang; David Slavin; Aaron Oki; Reynold Kagiwada
Semiconductor technology has seen rapid advances in recent years. Complementary?metal-oxide-semiconductor (CMOS) technology is providing tremendous digital processing power by integrating billions of transistors. Indium phosphide (InP) has bridged the terahertz frequency barrier. Gallium nitride (GaN) is offering unprecedented solid-state RF power across the microwave spectrum. Diverse, accessible heterogeneous integration (DAHI) allows engineers to take advantage of all of these advances by combining them along with other semiconductor technologies onto a single chip. DAHI offers the ultimate in RF, mixedsignal, and digital capability for future mobile applications that will demand smaller size and weight with lower power and cost.
compound semiconductor integrated circuit symposium | 2015
Naveen Daftari; Leland Gilreath; Andrew D. Smith; Minh Thai; Khanh Thai; Monte Watanabe; Yi-Cheng Wu; Charlie Jackson; Ashley Danial; Dan Scherrer; Tim LaRocca
The first reported reconfigurable wideband mm-wave CMOS based beam forming network IC is demonstrated. The IC consists of two independent inputs and two correlated outputs. Each of the four RF paths has 2 bits amplitude control and 3 bits phase control, as well as a wideband amplifier to maintain RF signal power. The measured RMS amplitude and phase error is less than 0.4dB and 4° respectively. Amplifier power gating is added for low-power modes and calibration. An addressable shift register core (ASRC) to command the beam forming IC is included. The ASRC provides intelligent control of adjacent III-V based chips. The IC is 5mmX5mm and consumes 45mW of DC power.