John W. Fattaruso

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >

Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation

One of the sources of nonlinearity in charge redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. While it is possible to address this problem through capacitor fabrication technology improvements, situations arise where it is more desirable to use circuit techniques. The conventional fully differential charge redistribution converter topology eliminates errors proportional to the capacitor linear voltage coefficient, but its comparator is subjected to the common-mode input signal. When converting unbalanced differential signals, linearity is achieved only with large comparator common-mode rejection. An alternative differential converter topology that isolates the comparator from the input common-mode signal, resulting in a common-mode rejection ratio of -73 dB, is presented. In addition, a circuit that cancels the error caused by the quadratic capacitor voltage coefficient is described. Measurements show that it is capable of increasing the converter linearity by an order of magnitude. >

Self-calibration techniques for a second-order multibit sigma-delta modulator

An oversampled modulator design that uses a second-order loop and a three-bit quantizer to exhibit low quantization noise is reported. Second-order loops are attractive because they are unconditionally stable and require only a third-order sinc filter in the decimation filter. Tone energy is significantly reduced in a multibit loop. In addition, a multibit quantizer avoids increased noise generation with input levels near full scale. The modulator uses digital self-calibration of the DAC (digital-to-analog coverter) capacitors to reduce their mismatch. High linearity and low noise are then simultaneously possible when random dynamic capacitor matching is used. The modulator is clocked at 6.144 MHz, and a 0.5-VRMS low-distortion sine wave at 2 kHz is applied at the input. The decimation filtering, with an oversampling ratio of 128-to-1, is performed by an external processor. >

A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

A compressing preamplifier, ADC, DAC, output driver and clock oscillator are implemented in a mixed-signal BiCMOS hearing-aid chip with digital filtering. 2.8 /spl mu/V input noise floor over the audio band and 0.02 % THD are achieved with 270 /spl mu/A total battery current.

MOS analog function synthesis

The design of a monolithic MOS parametric analog function synthesizer is described. The contour and voltage scaling of the nonlinear function to be synthesized are determined by a set of input bias voltage parameters, and are independent of temperature and processing variations. Experimental results showing synthesis precision on the order of 2% over temperature are presented. The particular application of generating a voltage that is a nonlinear function of chip temperature for compensation purposes is addressed.

Triangle-to-sine wave conversion with MOS technology

A description is given of MOS circuit design techniques for nonlinear analog circuits that perform a triangle-to-sine wave conversion. These techniques may also be applied to synthesizing other functions. Design techniques for compensating the conversion for variations in temperature, processing, and triangle wave amplitude are also presented. Results from simulation and monolithic circuit fabrication are reported which show that a sinusoidal approximation with a total harmonic content of 0.2% at 1 kHz is practical. The test circuit is powered from /spl plusmn/5 V supplies and displays a bandwidth of 1.1 MHz.

Polycide/metal capacitors for high precision A/D converters

The authors present a novel metal-to-silicide-polysilicon capacitor and compare it with metal-to-polysilicon capacitors and conventional polysilicon-to-polysilicon capacitors. Voltage coefficient data for these capacitor structures with oxide, oxide/nitride, oxide/nitride/oxide, and nitride dielectrics are also discussed. It is shown that when metal-to-silicided polysilicon capacitors are used, voltage coefficients of less than 4 p.p.m./V can be attained, which is considerably less than that obtained when metal-to-poly or conventional poly-to-poly capacitors are used. For high-precision A/D converters, this value will make possible accuracies of up to 18 bits through self-calibration.<<ETX>>

Highly porous interlayer dielectric for interconnect capacitance reduction

Hydrogen silsesquioxane (HSQ) is a low density material for intra-metal gapfill, that offers low permittivity for interconnect capacitance reduction. Films with k as low as /spl sim/2.2 preferentially form between tightly-spaced metal leads when cured at low temperature (<400/spl deg/C), and interlayer dielectric properties are stable from 1 MHz to 1 GHz. HSQ simplifies the process integration of low-k materials for high performance interconnect applications by using standard semiconductor spin-on production techniques. Use of porous HSQ as a gapfill dielectric dramatically reduces the capacitive coupling between metal leads, resulting in higher interconnect performance.

Low-voltage analog CMOS circuit techniques

As power supply voltages are driven down by digital power constraints, circuit techniques must evolve to preserve the precision of analog functions in a mixed-signal system. This paper reviews recent developments in low-voltage CMOS design of opamps and other critical analog blocks where high gain and signal-to-noise ratio are required.

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μm CMOS process and occupies a die area of 1.9 mm2.