Sami Kiriaki

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate. >

Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation

One of the sources of nonlinearity in charge redistribution analog-to-digital converters (ADCs) is capacitor voltage dependence. While it is possible to address this problem through capacitor fabrication technology improvements, situations arise where it is more desirable to use circuit techniques. The conventional fully differential charge redistribution converter topology eliminates errors proportional to the capacitor linear voltage coefficient, but its comparator is subjected to the common-mode input signal. When converting unbalanced differential signals, linearity is achieved only with large comparator common-mode rejection. An alternative differential converter topology that isolates the comparator from the input common-mode signal, resulting in a common-mode rejection ratio of -73 dB, is presented. In addition, a circuit that cancels the error caused by the quadratic capacitor voltage coefficient is described. Measurements show that it is capable of increasing the converter linearity by an order of magnitude. >

Self-calibration techniques for a second-order multibit sigma-delta modulator

An oversampled modulator design that uses a second-order loop and a three-bit quantizer to exhibit low quantization noise is reported. Second-order loops are attractive because they are unconditionally stable and require only a third-order sinc filter in the decimation filter. Tone energy is significantly reduced in a multibit loop. In addition, a multibit quantizer avoids increased noise generation with input levels near full scale. The modulator uses digital self-calibration of the DAC (digital-to-analog coverter) capacitors to reduce their mismatch. High linearity and low noise are then simultaneously possible when random dynamic capacitor matching is used. The modulator is clocked at 6.144 MHz, and a 0.5-VRMS low-distortion sine wave at 2 kHz is applied at the input. The decimation filtering, with an oversampling ratio of 128-to-1, is performed by an external processor. >

A 160 MHz analog equalizer for magnetic disk read channels

This prototype filter has five taps and operates at 160 MHz clock rate, dissipating 200 mW with 5 V supply. The filter occupies 1.35 mm/sup 2/ in BiCMOS with 0.8 /spl mu/m CMOS. It uses BiCMOS sample-and-hold (S/H) circuits to derive analog discrete-time samples, and CMOS time shared sign-sign LMS (SS-LMS) for coefficient adaptation. It improves on a previous analog signal shuffling structure by: (a) fast master S/H improves the dynamic performance and reduces effect of clock jitter on timing and gain recovery, (b) additional S/H amplifiers alleviate settling time requirements and reduce power, (c) time-interleaved LMS algorithm permits low-cost and low-power coefficient adaptation. DACs for taps and for dc offset cancellation are on-chip.

A 5 V, 16 b 10 mu s differential CMOS ADC

A fully differential charge redistribution analog-to-digital-converter (ADC) chip fabricated in a 5-V, 1.0- mu m CMOS process that includes polysilicide-to-metal capacitors, polysilicon resistors, and low-threshold n-channel transistors is discussed. The successive-approximation ADC uses self-calibration of capacitor, gain, and offset errors. Self-correction techniques are also used to eliminate first-order common-mode error and first- and second-order capacitor voltage dependence. A comparator topology minimizes comparator offset hysteresis.<<ETX>>