Ki Chang Kwean
SK Hynix
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Publication
Featured researches published by Ki Chang Kwean.
international solid-state circuits conference | 2006
Dong Uk Lee; Hyun Woo Lee; Ki Chang Kwean; Young Kyoung Choi; Hyong Uk Moon; Seung Wook Kwack; Shin Deok Kang; Kwan Weon Kim; Yong Ju Kim; Young Jung Choi; Patrik B. Moran; Jin Hong Ahn; Joong Sik Kih
A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process
Archive | 2004
Ki Chang Kwean
Archive | 2010
Je Yoon Kim; Ki Chang Kwean
Archive | 2005
Seung Wook Kwack; Ki Chang Kwean
Archive | 2004
Shin Deok Kang; Ki Chang Kwean
Archive | 2005
Ki Chang Kwean
Archive | 2008
Ki Chang Kwean
Archive | 2008
Ki Chang Kwean
Archive | 2015
Hee Jin Byun; Ki Chang Kwean
Archive | 2007
Ki Chang Kwean
