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Dive into the research topics where Ki-Kwan Park is active.

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Featured researches published by Ki-Kwan Park.


international electron devices meeting | 2014

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

R.-H. Kim; Byung-hee Kim; T. Matsuda; Jin-Gyun Kim; Jongmin Baek; Jong Jin Lee; J.O. Cha; J.H. Hwang; S.Y. Yoo; K.-M. Chung; Ki-Kwan Park; J.K. Choi; Eun-Cheol Lee; Sang-don Nam; Y. W. Cho; Hyoji Choi; Ju-Hyung Kim; Soon-Moon Jung; Do-Sun Lee; Insoo Kim; D. Park; Hyae-ryoung Lee; S. H. Ahn; S.H. Park; M.C. Kim; B. U. Yoon; S.S. Paak; N.I. Lee; J.-H. Ku; J-S Yoon

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.


international electron devices meeting | 2013

Superior Cu fill with highly reliable Cu/ULK integration for 10nm node and beyond

T. Matsuda; Jong Jin Lee; K. H. Han; Ki-Kwan Park; J.O. Cha; Jongmin Baek; T.-J. Yim; Dong-Chan Kim; Do-Sun Lee; Jin-Gyun Kim; Seungwook Choi; Eun-Cheol Lee; Sang-don Nam; Hyae-ryoung Lee; Y. W. Cho; Insoo Kim; B. H. Kwon; S. H. Ahn; J. H. Yun; Byung-hee Kim; B. U. Yoon; J.S. Hong; N.I. Lee; S. Choi; Hyon-Goo Kang; E. S. Chung

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.


international interconnect technology conference | 2015

High performance Cu/low-k interconnect strategy beyond 10nm logic technology

R.-H. Kim; Byung-hee Kim; Jin-Gyun Kim; Jong Jin Lee; Jongmin Baek; J.H. Hwang; J.W. Hwang; J. Chang; S.Y. Yoo; T.-J. Yim; K.-M. Chung; Ki-Kwan Park; T. Oszinda; Insoo Kim; Eun-Cheol Lee; Sang-don Nam; Soon-Moon Jung; Y. W. Cho; Hyunjun Choi; Ju-Hyung Kim; Sang-hoon Ahn; Sun-hoo Park; B. U. Yoon; J.-H. Ku; S.S. Paak; N.I. Lee; S. Choi; Hyon-Goo Kang; Eunseung Jung

CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.


international electron devices meeting | 2003

Alleviating electromigration through re-engineering the interface between Cu & dielectric-diffusion-barrier in 90 nm Cu/SiOC (k=2.9) device

Young Jin Wee; Soo Geun Lee; Won Sang Song; Kyoung-Woo Lee; Nam Hyung Lee; Ja Eung Ku; Ki-Kwan Park; Seung-Jin Lee; Jae Hak Kim; Joo Hyuk Chung; Hong Jae Shin; Sang Rok Hah; Ho-Kyu Kang; Gwang Pyuk Suh

Despite the initial success in integrating a 90 nm Cu/SiOC (k=2.9) device using the HSQ via-filler scheme, the reliability issues remain. By correlating electromigration (EM) with the moisture blocking capability of the dielectric-diffusion-barrier, we target the factors contributing to the moisture blockage, namely, the N and H-content within SiC. Consequently, increasing the N/H ratio in the SiCN film, we demonstrated a significant enhancement in EM reliability.


Archive | 2005

Method for forming interconnection line in semiconductor device and interconnection line structure

Kyoung-Woo Lee; Hong-jae Shin; Jae-Hak Kim; Young-Jin Wee; Seung-Jin Lee; Ki-Kwan Park


Archive | 2008

Semiconductor devices including trench isolation structures and methods of forming the same

Dong-Suk Shin; Seung-Jin Lee; Yong-kuk Jeong; Ki-Kwan Park


Archive | 2003

Method of forming dual damascene interconnection using low-k dielectric material

Jae-Hak Kim; Soo-Geun Lee; Ki-Kwan Park; Kyoung-Woo Lee


Archive | 2005

Method of forming interconnection lines for semiconductor device

Kyoung-Woo Lee; Hong-jae Shin; Jae-Hak Kim; Young-Jin Wee; Seung-Jin Lee; Ki-Kwan Park


Archive | 2005

Verbindungsstruktur und deren Herstellungsverfahren

Jae-Hak Kim; Kyoung-Woo Intell.Prop.Team Semiconduct.Busin Lee; Seung-Jin Lee; Ki-Kwan Park; Hong-jae Shin; Young-Jin Wee


Archive | 2005

Method of forming an interconnection line structure

Kyoung-Woo Intell.Prop.Team Semiconduct.Busin Lee; Hong-jae Shin; Jae-Hak Kim; Young-Jin Wee; Seung-Jin Lee; Ki-Kwan Park

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