Byung-hee Kim

4.2: Integrated Scan Driver with Oxide TFTs Using Floating Gate Method

An on-glass integrated scan driver is proposed for oxide thin film transistors TFTs with negative threshold voltage. A coupling capacitor and a TFT for setting the initial voltage to the gate of a TFT were added to minimize the off-state current. Simulated and measured results indicate that the proposed scan driver shows no ripple and fast rise time/fall time of scan outputs. Circuit operation was verified with a 14-inch AMOLED panel.

PMOS body-tied FinFET (Omega MOSFET) characteristics

In this paper, we introduce PMOS body-tied FinFet characteristics. For this work, the 0.1/spl mu/m design ruled SRAM technology was used. I/sub D/-V/sub DS/ characteristics show that /spl Omega/ MOSFET apparently has lower DIBL characteristics than conventional PMOS transistor. On current of the /spl Omega/ MOSFET is higher than that of conventional device and can be improved by optimising unit processes.

49.3: Oxide TFT Scan Driver with Dynamic Threshold Voltage Control

Oxide TFTs have a negative threshold voltage (Vth), which can become even more negative in response to DC or AC stress. Therefore, these voltage stresses can cause severe leakage current in a scan driver. In this paper, a scan driver with dynamic threshold voltage control (DTVC) is proposed to minimize the leakage current and enlarge operating margin. Effectiveness of DTVC was verified with a 14-inch AMOLED.

High-speed pixel circuits for large-sized 3-D AMOLED displays

— Large-sized active-matrix organic light-emitting diode (AMOLED) displays require high-frame-rate driving technology to achieve high-quality 3-D images. However, higher-frame-rate driving decreases the time available for compensating Vth in the pixel circuit. Therefore, a new method needs to be developed to compensate the pixel circuit in a shorter time interval. In this work, image quality of a 14-in. quarter full-high-definition (qFHD) AMOLED driven at a frame rate of over 240 Hz was investigated. It was found that image degradation is related to the time available for compensation of the driving TFT threshold voltage. To solve this problem, novel AMOLED pixel circuits for high-speed operation are proposed to compensate threshold-voltage variation at frame rates above 240 Hz. When Vth is varied over ±1.0 V, conventional pixel circuits showed current deviations of 22.8 and 39.8% at 240 and 480 Hz, respectively, while the new pixel circuits showed deviations of only 2.6 and 5.4%.

21.2: Driving Method for a 2D-3D Switchable AMOLED Display Using Progressive or Simultaneous Emission

A driving method has been developed for a 2D-3D switchable AMOLED using progressive emission PE or simultaneous emission SE. The proposed method is implemented by selecting PE mode for 2D to improve light emission ratio and SE mode for 3D to reduce left-right crosstalk without sacrificing luminance. This method also improves the contrast ratio by removing unnecessary light emission and can offer better uniformity by increasing the threshold voltage compensation time. A 240Hz-driven 30″ 3D AMOLED display was built and it was confirmed that there is no ELVDD surge current in the SE mode.

53.5: High-Speed AMOLED Pixel Circuit and Driving Scheme

An active matrix organic light emitting diode pixel circuit and its driving scheme for high frame frequency are proposed for implementation of a 3D display. The proposed pixel circuit can compensate the threshold voltage distribution of low temperature poly silicon-thin film transistors at high-speed operation of 240Hz or more. According to the simulation, current deviation of 1.73% and 3.94% are obtained at frame rates of 240Hz and 480Hz when Vth distribution is ±0.5 V.

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.

Superior Cu fill with highly reliable Cu/ULK integration for 10nm node and beyond

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.

50.3: Novel Self‐Aligned LDD/Offset Structure for poly‐Si Thin Film Transistors

A novel structure for poly-Si thin film transistors (TFTs) and its fabrication method were proposed to improve I-V characteristics of the TFTs by self-aligned lightly doped drain (LDD) / offset structure fabricated by formation of sidewall on both sides of the gate electrodes. In this structure, a capping layer is used to electrically isolate the gate lines from the data lines and to control the LDD/offset length. On forming the sidewall, the gate insulator was simultaneously etched to open source/drain region on the active poly-Si layer. In this work the LDD/offset structure was achieved by using only simplified 3-mask process, eliminating typical process steps for interlayer deposition and contact hole opening.

Highly manufacturable silicon vertical diode switches for new memories using selective epitaxial growth with batch-type equipment

Practical selectivity window of selective epitaxial growth (SEG) using a H2/SiH4/Cl2 cyclic chemical vapor deposition (CVD) system has been investigated with the batch-type vertical furnace equipment, replacing a conventional single-wafer H2/dichlorosilane/HCl CVD system. The process temperature was less than 700 °C, which is suitable for a low thermal budget process applicable to next-generation memories including vertical pn-diode switches. Selectivity loss is quantified by an in-line inspection tool to determine the practical number of selectivity losses. The H2/SiH4/Cl2 cyclic CVD system provides an excellent capacity of 40 wafers per batch. Selectivity loss, which is one of the most crucial features in the SEG process for the diode application, is controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and the practical number of selectivity loss is confirmed to be less than 100 in 200 mm wafers. Without high temperature annealing in hydrogen ambient, low temperature cyclic SEG in the batch reactor ensures the clean interface and improved crystalline quality of SEG-Si, as well as high throughput.