Young-Jin Wee

A novel Al-reflow process using surface modification by the ECR plasma treatment and its application to the 256 Mbit DRAM

A novel Al-reflow process with the electron cyclotron resonance (ECR) plasma treatment for the modification of underlayers was developed in a vacuum isolated sputtering equipment. The key feature of this technology is the introduction of the in-situ ECR plasma treatment for the modification of the surface characteristics such as surface morphology and stoichiometry of the TiN wetting/barrier layer. High wettability of the Al film was obtained on the ECR-treated TiN surface, producing a conformal Al film on the sidewall of the contact hole before the reflow process. Consequently, complete filling of contact holes with Al was achieved in deep sub-micron contact holes with a high aspect ratio. This study has demonstrated that the Al-reflow process can be extended to the process of the devices of 256 Mbit DRAM generation and beyond.<<ETX>>

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

Re-defining reliability assessment per new intra-via Cu leakage degradation

By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.

Electromigration reliability of dual damascene copper interconnect with different IMD structures

Electromigration behavior of dual damascene Cu interconnect has been investigated comparing PE-TEOS SiO/sub 2/ with fluorine doped SiO/sub 2/ (FSG). MTFs of FSG in both line and contact EM tests were significantly shorter than those of PE-TEOS. The higher compressive stress and fluorine of FSG dielectric are considered to affect the EM reliability performance of the confined Cu interconnect.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

Effect of mechanical strength and residual stress of dielectric capping layer on electromigration performance in Cu/low-k interconnects

We present the effect of mechanical strength and residual stress of dielectric barrier on electromigration performance in Cu/low-k interconnects. It has been discovered that mechanical strength and residual stress of dielectric capping layer have a great role on EM performance. The use of mechanically strong dielectric capping material with high residual compressive stress in Cu/low-k interconnects improves a structural confinement of Cu line. Also, it helps tensile stress level decrease near via bottom and compressive stress level increase at Cu beneath SiCN along Cu line. Reduction of tensile stress at via bottom would effectively suppress void nucleation and growth. Moreover, increase of compressive stress in Cu beneath SiCN alleviates Cu migration through that pathway, leading to a longer lifetime of interconnect component.

Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).

Highly electromigration-resistive via structure using Al-reflow for multi-level interconnection

A highly reliable double-level interconnection has been achieved by applying Al-reflow process to via level. The outgassing species from IMD materials were investigated by RGA and high temperature pre-degassing of IMD at 500 °C prior to Al deposition on vias is found to be essential to minimize via poisoning. When Al-reflow process was applied to vias, superior electromigration resistance of both via and metal lines was obtained with non-barrier structure, Al/Al, and thicker Ti barrier layer resulted in worse electromigration resistance. TEM micrographs of the via interfaces revealed that when Ti barrier layer was used in Al-reflow process, the high temperature reflow step produced agglomeration of Al×Ti at the via interface by the reaction between Ti and Al. The longer electromigration lifetime of Al-reflowed vias without Ti barrier layer is attributed to the elimination of Al step coverage as well as more homogeneous via interfaces.

Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.

Underlayer type dependence of EM threshold in Al-Cu interconnect

The underlayer type dependence of the electromigration (EM) threshold has been investigated in the Ti (bottom)/Al-Cu and the Ti (bottom)/TiN (top)/Al-Cu structures. From the activation energies of Cu-drift and Al-drift, the beneficial effects of Ti as an Al underlayer is shown to be associated not only with higher residual tensile stress but also with higher compressive Al-Cu yield stress. The implications of underlayer optimization are also discussed.