Chih-Hang Tung

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component exx and the vertical strain component ezz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-...

Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement

We report the demonstration of 25 nm gate length L_G tri-gate FinFETs with Si_0.99C_0.01 source and drain (S/D) regions. The strain-induced mobility enhancement due to the Si_0.99C_0.01 S/D leads to a drive current I_Dsat improvement of 20% at a fixed off-state current I_off of 1times10^-7 A/mum. With additional channel strain engineering, FinFETs incorporating Si_0.99C_0.01 S/D and a tensile-stress silicon nitride (SiN) capping etch-stop layer (ESL) achieve an I_Dsat enhancement of 56%

In Situ Surface Passivation and CMOS-Compatible Palladium–Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs

In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane treatment), alternative gold-free palladium-germanium (PdGe) source and drain (S/D) ohmic contacts, and silicon plus phosphorus coimplanted S/D regions. With the novel in situ surface passivation, excellent capacitance-voltage characteristics with low-frequency dispersion and small stretch-out can be achieved, indicating low interface state density. This surface-channel GaAs device exhibits excellent transistor output characteristics with a high drain current on/off ratio of 105 and a high peak electron mobility of 1230 cm2/V ldr s. In addition, gold contamination concerning CMOS technology can be alleviated with the successful integration of low-resistance PdGe ohmic contacts.

Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement

We report a novel strained n-channel transistor structure featuring silicon-carbon (SiC) source and drain (S/D) regions formed on thin body SOI substrate. The SiC material is pseudomorphically grown by selective epitaxy and the carbon mole fraction incorporated is 1%. Lattice mismatch between SiC and Si results in uniaxial tensile strain in the Si channel region which contributes favorably to electron mobility enhancement. Drive current IDsat enhancement of 25% was observed for 90 nm gate length LG transistors, and IDsat enhancement of up to 35% was observed at LG of 70 nm. In addition, drive current enhancement shows dependence on device width and channel orientation. All transistors were formed on (001) SOI substrates. The largest IDsat enhancement is observed for transistors with the [010] channel orientation

Investigation of silicon-germanium fins fabricated using germanium condensation on vertical compliant structures

We report the formation of defect-free SiGe vertical heterostructures using Ge condensation on vertical SiGe structures. To evaluate the effectiveness of substrate compliance in vertical structures, SiGe fins of various widths were subjected to Ge condensation. This formed vertical fin heterostructures comprising a SiGe core region sandwiched by Ge-rich regions. Using cross-sectional transmission electron microscopy (TEM), wide fins were found to contain more dislocations than narrower fins, in which we observed few or no dislocations. Lattice strain analysis using high-resolution TEM image analysis was used to confirm that strain relaxation has occurred. In the wide fins (noncompliant substrate), strain relaxation was dislocation mediated. In the narrow fins, substrate compliance enabled strain relaxation in the Ge-rich layer with reduced dislocation formation. Hence, we also demonstrated the formation of a strain-relaxed homogeneous SiGe fin (∼90% Ge concentration) with no observable dislocations.

Strained n-Channel FinFETs Featuring In Situ Doped Silicon–Carbon

Phosphorus in situ doped (Si1-yCy) films (SiC:P) with substitutional carbon concentration of 1.7% and 2.1% were selectively grown in the source and drain regions of double-gate -oriented (110)-sidewall FinFETs to induce tensile strain in the silicon channel. In situ doping removes the need for a high-temperature spike anneal for source/drain (S/D) dopant activation and thus preserves the carbon substitutionality in the SiC:P films as grown. A strain-induced enhancement of 15% and 22% was obtained for n-channel FinFETs with 1.7% and 2.1% carbon incorporated in the S/D, respectively.

(\hbox{Si}_{1 - y}\hbox{C}_{y})

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.

Source and Drain Stressors With High Carbon Content

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current IDSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.

Strained p-Channel FinFETs With Extended

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

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We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si1-yCy) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium-aluminum oxide high-k gate dielectric. Due to the lattice mismatch between Si0.99C0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/mum, the Sii-j/C1-yCy S/D N-MOSFET having a width of 4.7 mum achieves a drive current Josat enhancement of 16% over a control N-MOSFET. This iDsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length LG due to an increased strain level in the transistor channel as the Si1-yCy S/D stressors are placed in closer proximity. Slightly improved series resistance with Si1-yCy S/D regions in a strained N-MOSFET accounted for approximately 2% IDsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions.