Kirk Prall

Scaling Non-Volatile Memory Below 30nm

The future scaling challenges of non-volatile memories for 32 Gb+ using 30 nm and below feature sizes are discussed. The key challenges reviewed include structural integrity, floating gate scaling, floating gate replacement, noise and variation. Future trends are discussed.

19.7 A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology

Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (<;1Gb) while those reporting high-density arrays (>8Gb) were accompanied by relatively low read and write performance [1-5]. This work describes a 16Gb ReRAM designed in a 27nm node, with a 1GB/s DDR interface and an 8-bank concurrent DRAM-like core architecture. High parallelism, a pipelined data-path architecture and innovations such as concurrent set/reset verify combine to achieve 200MB/s write and 1GB/s read throughputs in a high-density device.

25nm 64Gb MLC NAND technology and scaling challenges invited paper

A highly manufacturable 25nm 64Gb NAND technology has been developed. Many physical and electrical scaling challenges were overcome. Severe scaling challenges have to be overcome to continue NAND scaling.

Process integration of a 27nm, 16Gb Cu ReRAM

A 27nm 16Gb Cu based NV Re-RAM chip has been demonstrated. Novel process introduction to enable this technology include a Damascene Cell, Line-SAC Digit Lines filled with Cu, exhumed-silicided array contacts, raised epitaxial arrays, and high-drive buried access devices.

An Update on Emerging Memory: Progress to 2Xnm

This paper will give an update on the status of emerging memory (EM) and potential markets. The more popular EM technologies will be reviewed, including PCM, RRAM, and STRAM. The biggest challenges for each technology will be highlighted.

Suppression of reverse biased diode leakage by MeV ion implantation

MeV Ion implantation has proven useful for many applications, such as latch-up suppression, SER reduction, and buried layer formation. MeV ion implantation can also be used to form a minority carrier diffusion barrier to reduce reverse bias diode leakage, particularly at high temperatures. The reduction in diode leakage has applications in DRAMs, CCDs, etc. The use of a MeV implanted diffusion barrier improves the ability to scale DRAM cell capacitance.<<ETX>>

A semiconductor memory development and manufacturing perspective

Semiconductor memories are growing in importance as they are now fundamental in every electronic system and offer new manufacturing and development challenges and opportunities. From a manufacturing point of view, the industry has undergone consolidation and today very few players are able to supply the high wafer volumes required by the global market. From a technology development point of view, new applications requiring lower power, higher memory density and improved performance creates opportunities for alternative memory technologies. Moreover, the shift to 3-dimensional integration and to new system architectures result in both manufacturing and technology challenges.

Engineering a planar NAND cell scalable to 20nm and beyond

Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.

Trends in memory technology - reliability perspectives, challenges and opportunities

As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.

Benchmarking and Metrics for Emerging Memory

Comparison of the dominant emerging memory technologies at the fundamental cell level will be presented. Metrics will be discussed and the technologies will be compared with the objective of judging the suitability for high density memory applications.