Brandon C. Barnett

Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution

This paper analyzes the performance of different interconnect technologies for on-chip clock distribution, including conventional, three-dimensional, optical, and radio frequency interconnects. Skew, power, and area usage were estimated for each of these technologies based on the 2001 International Technology Roadmap for Semiconductors. Our results indicate that most of the skew and power are associated with local clock distribution. Consequently, since the alternative clock distribution approaches that have been proposed focus on global clock distribution, we have not found significant advantages over conventional clock distribution in terms of skew and power. Furthermore, it was found that low skews could be attained with conventional clock distribution schemes if the clock signals are not scaled down.

Optical I/O technology for digital VLSI

We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).