Xiaoning Qi

High-frequency characterization of on-chip digital interconnects

On-chip inductance is becoming increasingly important as technology continues to scale. This paper describes a way to characterize inductive effects in interconnects. It uses realistic test structures that study the effect of mutual couplings to local interconnects, to random lines connected to on-chip drivers, and to typical power and ground grids. The use of S parameters to characterize the inductance allows a large number of lines to be extracted while requiring only a small overhead measurement of dummy open pads to remove measurement parasitics. It also enables direct extraction of the frequency-dependent R, L, G, C parameters. The results are summarized with curve-fitted formulas of inductance and resistance over a wide range of line spacings and line widths. The significance of the frequency dependence is illustrated with transient analysis of a typical repeater circuit in a 0.25-/spl mu/m technology. A model that captures the frequency dependency of the extracted parameters accurately predicts the performance of a new inductance-sensitive ring oscillator.

On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.

On-chip inductance modeling of VLSI interconnects

At gigahertz frequencies, long interconnect wires exhibit transmission line behavior. Using copper and wider wires for major signal and power/ground lines, inductive impedance (j/spl omega/L) could become comparable to the resistive component of the wire (R). Due to the inductance, delay increases, over-shoot occurs, and inductive crosstalk can no longer be ignored. Inductive effects were recently demonstrated in 4 mm-long lines in a 0.25 /spl mu/m process. The extracted delays of a typical clock line from this test chip are shown. While the delay is a linear function of line length, the RC delay increases with the square of the line length. As a result, the inductive effects are actually more prominent for lines with intermediate lengths. The inductive effects for the intermediate length buses as well as local clocks must be considered. As technology is scaled, the gate delay time will continue to be reduced while the delay of short, low-resistive clock lines will remain constant. The inductive effects will therefore become prominent for progressively short lines. The article shows simulated inductance effects on crosstalk. Larger coupling and ringing effects are observed when inductive coupling is included in the simulation. Currently, the inductive effects are only considered for a few global clocks and buses, which is insufficient for future designs. Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of todays integrated circuits. To model the inductive effects of intermediate-length buses as well as local clocks, a fast automated inductance extraction and verification tool is necessary.

A fast 3D modeling approach to electrical parameters extraction of bonding wires for RF circuits

Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF applications. An approach to fast three-dimensional (3D) modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the frequency response of bonding wires. To verify simulation accuracy, test structures have been made and measured. Excellent agreement between simulated and measured data is achieved for frequencies up to 10 GHz. The model is well suited for the design and analysis of circuits for cellular phone communication (i.e., order 2 GHz) and future wireless communication (i.e., order 5 GHz).

Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits

This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chips power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.

Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies

Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.

Line inductance extraction and modeling in a real chip with power grid

A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 0.25-/spl mu/m CMOS technology. A new ring oscillator for the extraction of signal delay and characteristic impedance is demonstrated. The increase of signal delay due to mutual inductance of clock lines is measured directly with S-parameter characterization techniques.

A New Simulation Method for NBTI Analysis in SPICE Environment

This paper presents a simulation framework for reliability analysis of circuits in the SPICE environment. The framework incorporates the degradation of physical parameters such as threshold voltage (Vtp) into circuit simulation and enables the design of highly reliable circuits. The parameter degradation is based on the numerical solution for the reaction-diffusion (R-D) mechanism, which is a general model applicable to various reliability effects such as NBTI, HCI, NCS, and SEE. In particular, the accuracy and efficiency of this method was verified for NBTI degradation with 130nm experimental and simulation data over a wide range of stress voltages and temperature. The model also accurately captures the dependence of NBTI on multiple diffusion species (H/H2), key process (Vth, tox) and environmental parameters (VDD, temperature). The circuit level performance of this method is verified with silicon data from ring-oscillator circuit. We also investigated the predicted impact of NBTI on representative digital circuits

Device level modeling of metal-insulator-semiconductor interconnects

A rigorous model for metal-insulator-semiconductor (MIS) interconnects is presented based on device level simulation results. At the device level, the motion equations of charged carriers and Maxwells equations are simultaneously solved using a finite element scheme and Newtons method. Simulations provide detailed information regarding field-carrier interactions, semiconductor substrate loss and nonlinearity, as well as the slow-wave effect, external bias effect, and screening effect of the charged carriers. An equivalent circuit model of MIS interconnects is established using an energy-based approach. The model consists of an equivalent transmission line that mimics the energy transport characteristics of the actual MIS interconnect, and provides a generalized nonlinear and electronic tunable circuit model suitable for both small-signal and large-signal analysis. Examples are presented to illustrate capabilities and efficiency of the method as well as properties of the equivalent circuit model.

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized