Kisup Chung

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Essential edge protection techniques for successful multi-wafer stacking

3D edge protection for wafer scale stacking using oxide bonding has been demonstrated with readily available CMOS compatible processes. Edge voiding has been shown to vastly reduce as well CMP edge removal. By utilizing edge protection schemes such as this, in combination with other approaches for bevel/edge protection for wafer thinning [4], wafer edges can be preserved with minimal additional processing complexity to enable multi-wafer 3D stacking and technologies such as Backside Illuminated Image Sensors (BSI) [9] and 3Dm, all of which can benefit from such an approach.

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

Under-layer effects for block levels: are they under control?

Challenges in block levels due to the dilemma of cost control and under-layer effects have been addressed in several papers already, and different approaches to solve the issue have been addressed. Among the known approaches, developable BARC and under-layer aware modeling are the most promising. However, in this paper we will discuss and explain the limitation inefficiency of both methods. In addition, as more block levels are employing etching step, the under-layer dependent etch behavior that we see in some of the block levels is also discussed. All these place great challenges for block level process development. We discuss here possible solutions/improvements including: developable BARC (dBARC) thickness optimization for specific under layers; Simplified model based corrections for lith and etch. This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

Development of TiO2 containing hardmasks through PEALD deposition

With the increasing prevalence of complex device integration schemes, tri layer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination, and are limited in their ability to scale down thickness without comprising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of PEALD deposited TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a tri layer scheme patterned with PEALD based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited vs a spin-on metal hardmask.

Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition

Abstract. With the increasing prevalence of complex device integration schemes, trilayer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination and are limited in their ability to scale down thickness without compromising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of plasma-enhanced atomic layer deposited (PEALD) TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a trilayer scheme patterned with PEALD-based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited versus a spin-on metal hardmask.

CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond

We demonstrate a record-low EOT (equivalent oxide thickness) of 0.8 nm for a metal-insulator-metal (MIM) decoupling capacitor, which is compatible with back-end-of-line (BEOL) processing. This results in 2-plate MIM capacitance density of 43 fF/um2, and leakage current density (Jg) of 5 fA/um2 at 1V, 125 oC. Moreover, we identify that symmetry of CV/IV/TDDB characteristics for both positive and negative bias polarities is a key consideration for stacking more than one MIM capacitor for further capacitance density increase. We develop a novel tri-layer high-k stack with buffer layers between HfO2 and metal electrodes, which substantially improves the electrical bias symmetry, and achieve Vuse = 1.32 V (10 yr/1 ppm/1 cm2/125 oC) at EOT = 0.8 nm. These results should support record stacked-MIM (> 2-plate) capacitance densities, with sub-nm EOT, for the 7 nm node and beyond.