Keunmyung Lee

Modeling and analysis of multichip module power supply planes

A method that would allow accurate modeling of arbitrarily shaped planes with bypass capacitors has been developed. It is compatible with a SPICE-based modeling method for the rest of the power supply hierarchy and the devices. A modified SPICE is used to accommodate distributed circuits. The distributed circuits are built with microwave analysis software and connected to SPICE by s-parameter files. The modeling process is described and examples of thick and thin-film power supply planes are presented with comparison to measured results. The method is used to explore potential design choices for a large MCM with many simultaneously switching drivers. >

Accurate power supply and ground plane pair models

This paper derives the theory and method for the two dimensional discrete transmission line (TL) and coupled transmission line (CTL) models, including the high frequency skin effect for an arbitrarily shaped plane pair in a multiple dielectric layer structure. The null or peak of the S parameter frequency response represents the test port interaction with the resonant standing wave of these planes at that frequency. The resultant S parameter data of these models can be condensed into a simpler N port equivalent circuit to represent a larger hierarchical power and ground plane network for fast simulation.

Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced. >

A bare-chip probe for high I/O, high speed testing

The authors describe a bare chip probing fixture for temporary interconnection of a VLSI tester to a die. It is capable of connecting to an area array of die pads, can operate beyond 1 GHz, and is extensible to 1000 signal I/Os. This probe has been adapted to an existing VLSI tester by attaching it to a custom DUT board and has been used to test operational silicon. The fixture consists of a four metal layer membrane probe which is an enhancement to a previously described burn-in fixture with a novel alignment scheme and no-wipe contacting buttons. The probe is electrically connected to the DUT PCB with an array of button connections, and board I/O is through coaxial cables to the tester. A mechanical structure provides alignment of the PCB, button connector, and membrane probe while providing controlled pressure between the membrane and die, and at the same time cooling the die. The authors describe the electrical performance of the interconnect and the results of testing a circuit toggling at up to 1 GHz, compare them with another probing solution and describe future improvements contemplated. In addition, they briefly describe the potential for use as a very fast bare chip burn-in fixture. >

IPDA: interconnect performance design assistant

IPDA is a generic interconnect performance design assistant that integrates a finite-difference numerical simulation method, linear interpolation algorithm, interactive performance synthesis methodology, and lossless/lossy transmission-line SPICE modeling capability into a spreadsheet-style graphical user interface. The algorithm, implementation, and methodology of IPDA are described and an application example is discussed. Although the authors describe electrical performance measures for given geometry and material parameters of conductors and dielectrics, IPDA can be customized for other packaging measures such as reliability and thermal and cost effects through spreadsheet interface and calculations. IPDA assists users in selecting interconnect technologies for design-for-performance goals and also in optimizing interconnect performance designs for the full hierarchy of packaging including IC/multichip module/printed circuit board/lead-bonding/via interconnect designs.<<ETX>>

Parameterized SPICE subcircuits for submicron multilevel interconnect modeling

A parameterized interconnect modeling system which provides VLSI designers with a direct link between finite-difference 2-D/3-D capacitance simulators and SPICE simulators is described. In this way, both the device modeling and the interconnect modeling are parameterized, and the time needed to generate SPICE inputs is estimated to decrease by two or three orders of magnitude with this approach.<<ETX>>

A comparison of power supply planes in thick and thin film MCM's

A method that would allow accurate modeling of arbitrarily shaped planes with bypass capacitors has been developed and verified with thick and thin film MCM substrates. The method is used to explore potential design choices for a large MCM with many simultaneously switching drivers.

A method to reduce the peak current density in a via

A new method to alleviate the current crowding problems in the via connect of VLSI is presented. Current crowding in advanced metal systems may cause long term reliability problems for integrated circuits because the mean time to failure due to electromigration decreases as the maximum current density increases. The FCAP3 program (three-dimensional Poisson equation solving program) is used to study current flow in three-dimensional metal structures such as vias.

Methodology in Computer-Aided Design for Process and Device Development

The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.

A Systematic Study of Transistor Design Traae-offs

The ability to manufacture circuits at, or near, fundamental density and speed limits is affected by the sensitivity of circuit parameters to variations in the manufacturing process, and by the ability to achieve tight control of the manufacturing process. Modifications of device or circuit design can alter the various dependencies, so that parts of the process that are intrinsically more controllable determine critical circuit properties. Critical dimensions determined by a series of steps (mask-making, exposure, develop, etch) are typically held to + /- 20%. Various ion implant doses and depths can be controlled to + /- 2% to 5%. For example, if there is an absolute minimum for channel length, then the circuit design must be set at L min +ΔL, where the yield of devices with L >L min is satisfactory and ΔL is a measure of the process variation with gate line width. L min must also allow for some overlap of the gate to source and drain. If the minimum channel length is set by a reliability factor, then the design target is determined by allowable early field failures rather than the allowable yield. This illustrates the difficulty in understanding the problems associated with scaling critical dimensions to less than 0.5 μm.