John L. Moll

A Bird's Beak Free Local Oxidation Technology Feasible for VLSI Circuits Fabrication

This paper presents a birds beak free and fully recessed local oxidation-isolation structure employing only conventional LSI processing techniques; no additional masking step is required. A SideWAll Masked Isolation (SWAMI) process employing anisotropic plasma silicon etching and anisotropic plasma silicon nitride etching was implemented to form this new isolation structure. The SWAMI isolation scheme almost completely eliminates the reduction in effective channel width from drawn mask dimensions. The effective channel width obtained with the SWAMI isolation structure is independent of field-oxide thickness unlike the conventions LOCOS process. Fabrication technology and device characteristics of MOSFETs fabricated with the SWAMI isolation structure will be compared with the conventional LOCOS isolated MOSFETs.

Patterned implanted buried‐oxide transistor structures

Metal‐oxide‐semiconductor field‐effect transistors have been fabricated with a buried‐oxide layer implanted under only the source and drain regions. Tungsten selectively chemically vapor deposited over the polycrystalline‐silicon gate electrode limited the oxygen‐implanted area and provided a self‐aligned structure. The surface of the source and drain regions was raised above that of the channel by the implanted oxide. The buried oxide formed under the source and drain regions joined smoothly with the surrounding field oxide. Some additional oxide was formed beneath the thermally grown field oxide by the implanted oxygen, and significant field oxide appears to have been removed by sputtering during the implantation. A simplified, nonoptimum, transistor‐fabrication process produced depletion‐mode, n‐channel devices which exhibited transistor action.

Physical and technological limitations and their optimization in submicron ULSI interconnect

The trend of the performance degradation, noise and reliability issues and their potential solutions are analyzed for submicron ULSI interconnect lines. The analysis shows that a copper (Cu) line will improve electromigration, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improves the interconnect delay and electromigration, but increases the cost of system packaging. The optimum approach a combination of additional layers of nonscaled metal lines in a higher level and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.<<ETX>>

Technological limitations in submicron on-chip interconnect

The trend of the performance degradations, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm (HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters for HIVE, shows that a copper (Cu) line will improve the electromigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigration, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectric, and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.

Methodology in Computer-Aided Design for Process and Device Development

The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.

A Systematic Study of Transistor Design Traae-offs

The ability to manufacture circuits at, or near, fundamental density and speed limits is affected by the sensitivity of circuit parameters to variations in the manufacturing process, and by the ability to achieve tight control of the manufacturing process. Modifications of device or circuit design can alter the various dependencies, so that parts of the process that are intrinsically more controllable determine critical circuit properties. Critical dimensions determined by a series of steps (mask-making, exposure, develop, etch) are typically held to + /- 20%. Various ion implant doses and depths can be controlled to + /- 2% to 5%. For example, if there is an absolute minimum for channel length, then the circuit design must be set at L min +ΔL, where the yield of devices with L >L min is satisfactory and ΔL is a measure of the process variation with gate line width. L min must also allow for some overlap of the gate to source and drain. If the minimum channel length is set by a reliability factor, then the design target is determined by allowable early field failures rather than the allowable yield. This illustrates the difficulty in understanding the problems associated with scaling critical dimensions to less than 0.5 μm.

SUPREM III Application

SUPREM III has emerged as the most widely used process simulator. The authors of SUPREM III have attempted to include the most up-to-date physically based process models that are currently available and suitable for computer simulation. Innumerable research hours have gone into the development of the various models and fitting parameters. However a silicon process, whether it is bipolar, NMOS, or CMOS, is an extremely complicated entity. There are several problems inherent in the SUPREM process models.

Examples of Parasitic Elements Simulation

In this chapter, the examples of parasitic component simulations are presented. The problems are solved by the appropriate simulation tools discussed in Chapter 4 and the other tools such as SUPREM, GEMINI, and SUPRA. Section 15.2 covers two-dimensional problems and section 15.3 deals with the problems which have to be solved by three-dimensional simulation. The experimental verification of the simulation results are also discussed.

Simulation Techniques for Advanced Device Development

In this chapter, the basic simulation techniques for advanced MOS device development will be described. First of all, the basic device physics of MOSFET is presented. The discussion will be in very simple terms, although sufficient to allow the process engineers to understand the basic characteristics of MOSFETS and their significance. The techniques of generating the device parameters are then presented. Also to be discussed are the short channel effects such as drain-induced barrier lowering. Simulations are used to reveal details of these phenomena. The relationship between process parameters and device characteristics are discussed. Simulated results are compared with experimental results. The SUPREM, GEMINI and PISCES programs are used for simulating the device characteristics.

A Study of LDD Device Structure Using 2-D Simulations

In this chapter, analysis and design of LDD (Lightly Doped Drain) devices using two-dimensional device simulation and experiments will be described to illustrate the usefulness and necessity of using computer aided design tools in the fabrication of VLSI devices. First, the problem of high electric field in VLSI devices and the use of LDD device as a possible solution is discussed. The fabrication and simulation of LDD device is then described. Finally, the performance, characteristic, physics and design considerations of LDD devices are presented in detail.