Jun Etoh

A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production. >

Power Reduction Techniques in Megabit DRAM's

Power dissipation in dynamic random-access memories (DRAMs) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage bouncings, temperature variation, and threshold-voltage deviation due to the process fluctuation, while maintaining CMOS-DRAM process compatibility. Moreover, feedback-loop stability and frequency response are maintained by ensuring a phase margin of 55° at a unity-gain frequency of 10 MHz using compensation through zero insertion. Implementation of these new circuits in a 16-Mb CMOS DRAM is reported

Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMs

A new reference voltage generator with ultralow standby current of less than 1 /spl mu/A is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-/spl mu/m process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm//spl deg/C from room temperature to 100/spl deg/C, and output noise of less than 12 mV for 1 V/sub p/spl minus/p/ V/sub cc/ bumping are achieved. These results are sufficient for achieving high-density battery operated DRAMs with low active and data-retention currents comparable to SRAMs. >

A 1.5 V DRAM for battery-based applications

The authors report low-power, high-signal-to-noise-ratio (SNR) 16 Mbit DRAM (dynamic RAM) techniques which allow 1.5-V battery operation. To reduce power consumption, the data-line voltage swing is the sum of the threshold voltages for nMOS and pMOS transistors in the sense amplifier. A plate-pulse circuit technique, a three-level word pulse, and a 3.4- mu m/sup 2/ data-line shielded STC cell enhance SNR in the memory array. The main features of the DRAM are compared with those of the SNB (storage-node-boosted) technique and a conventional half-V/sub CC/ circuit technique.<<ETX>>

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized. >

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved. >

A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

A 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b CMOS DRAM characterized by a twisted driveline sense-amplifier (TDSA) scheme and a multiphase drive circuit which enable faster access time and a smaller peak power supply current, respectively, is described. The implementation of an initialize mode with CAS-before-RAS (CBR) logic control, which reduces the memory-chip initialization time by almost a thousand times, is also discussed. The chip measures 6.38/spl times/17.38 mm/SUP 2/ and has been fabricated by using double-well CMOS technology with a minimum design rule of 0.8 /spl mu/m. A typical access time of 65 ns and a peak power supply current of less then 150 mA have been obtained.

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within +or-0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to +or-50 mV at an ambient temperature up to 120 degrees C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures. >

Low-power chip interconnection by dynamic termination

A low-power dynamic termination scheme is proposed and demonstrated as a way to reduce power dissipation for high-speed data transport. In this scheme, the transmission lines are terminated only if the signals change. The gate of a switching MOS transistor connected to a termination resistor is driven by differentiating the transmission signal with a resistor and a capacitor. The power dissipation of the terminating resistor can be reduced to 1/5 in the conventional determination scheme, and overshoot can be reduced to 1/5 that in the open scheme. This scheme is promising for use with palm-top equipment, facilitating high-speed low power operation. >