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Featured researches published by Fumio Baba.


international solid-state circuits conference | 1985

A 1Mb DRAM with 3-dimensional stacked capacitor cells

Yoshihiro Takemae; T. Ema; M. Nakano; Fumio Baba; T. Yabu; Kiyoshi Miyasaka; K. Shirai

pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the


international solid-state circuits conference | 1983

A 35ns 64K static column DRAM

Fumio Baba; Hirohiko Mochizuki; T. Yabu; K. Shirai; Kiyoshi Miyasaka

A 64K by l b DRAM with multiplexed address inputs, packaged in a standard 300-mil wide 16 pin DIP, but with only one address strobe clock (RAS), will be reported. After one row address is selected with the RAS clock, as in normal multiplexed devices, column address selection (one of the 2561, boundarylrow) can be performed in a manner similar to static memory: data from the output changes in accordance with the change of column address without an address strobe clock. Access time from the columnzdress, and cycle time are typically 3511s. The deaffords CS (Chip select) instead of column address strobe (CAS), enabling or disabling the output at high speed. Typical chip select access time is less than 12ns. In write operation the falling edge of write enable (WE) latches the column address and Data In, and the write operation period extends automatically to the time when the device indicates the completion of writing; write time out. Following read or write operation starts immediately according to the state of WE. Figure 1 illustrates the concept of static column operation. The storage cells, sense amplifiers, and row decoders are almost the same as those of current 64K DRAMS. The sense amplifiers are fully dynamic with active pull up circuits. Word lines are pushed above Vcc to utilize the full charge of cells.


Archive | 1994

Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package

Atsushi Hatakeyama; Fumio Baba; Junichi Kasai; Mitsutaka Sato


Archive | 1980

Semiconductor devices having fuses

Hirohiko Mochizuki; Masao Nakano; Fumio Baba; Tomio Nakano; Yoshihiro Takemae


Archive | 1987

Dual-port semiconductor memory device

Hiroshi Nagayama; Fumio Baba


Archive | 1994

Semiconductor memory device having information indicative of presence of defective memory cell

Fumio Baba


Archive | 1983

Clock generating circuit providing a boosted clock signal

Fumio Baba


Archive | 1983

Block-divided semiconductor memory device

Fumio Baba


Archive | 1979

Semiconductor device having cross wires

Fumio Baba; Kiyoshi Miyasaka; T. Yabu; Jun-ichi Mogi


Archive | 1988

Semiconductor memory device having a register

Fumio Baba; Kazuya Kobayashi; Seiji Enomoto; Hiroaki Ogawa

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