T. Yabu

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

The authors describe circuit techniques for wide input/output (I/O) data path and high-speed 64-Mb dynamic RAMs (DRAMs). A hierarchical data bus structure using double-level metallization has been developed to form 64-b parallel data bus lines without increasing the chip size. A current-sensing data bus amplifier, developed to sense the 64-b data bus signal in parallel, has made the wide I/O data path structure possible. A direct-sensing type column gate circuit with the READ/WRITE separated select line scheme achieves 40-ns RAS access. A shielded bit-line three-dimensional stacked-capacitor cell with a double-fin storage capacitor stores sufficient charge while the bit-line capacitance shows a reasonable value for sensing the data. >

3-dimensional stacked capacitor cell for 16 M and 64 M DRAMS

A second-generation three-dimensional stacked capacitor cell has been developed. This cell has two significant features. One is that the three-dimensional feature of the storage capacitor has been considerably enhanced by means of a fine structure. The other is that bit lines have been formed before storage capacitor formation. Either of these features will lead to the realization of 16 M DRAMs (dynamic random-access memories), and both will be necessary to realize 64 M DRAMs.<<ETX>>

A 1Mb DRAM with 3-dimensional stacked capacitor cells

pads in the center of the chip, permit assembly within a 300mil 18 pin plastic DIP and 300mil26 pin plastic Small Outline J-lead package (SOJ). The cell structure is shown in Figure 1. First layer polycide forms the wordline. The second layer poly-Si, which forms the storage node, is extended over its own wordline and the next wordline. The third layer poly-Si, which forms the cell plate, is spread over the second layer poly-Si. The cell capacitor is formed between the second and third layer poly-Si. Bitline is formed by AI. Since the capacitor is formed over the wordlines, the address The chip layout, with peripheral circuitry and some of the

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K*8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8- mu m CMOS process technology. Standby power is 25 mu W, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8*8.5- mu m/sup 2/ cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses alpha -particle-induced soft errors. The chip size is 7.6*12.4 mm/sup 2/. >

A 64K DRAM with 35 ns static column operation

A 64K dynamic RAM with a function mode similar to static memory operation is described. The device has multiplexed address inputs and a one-address strobe clock (RAS). After a row address is applied to the device, column selection is performed as in static memory, resulting in fast cycle time and simplicity of use. Column address access time and cycle times of 35 ns are achieved. The device has some other functions to reduce critical timings. Address transition detector circuits are used for column selection. An improved column decoder is provided to allow column address input skew. The device uses NMOS single transistor memory cells and is packaged in a standard 300-mil 16-pin DIP.

A sub 100ns 256Kb DRAM

A 256K DRAM with nibble-mode and<tex>\overline{CAS}</tex>before<tex>\overline{RAS}</tex>refresh will be described. Triple-poly-si processing is used only with 2.5μ layout rules for a die size of 34.1mm².

A 19ns memory

A CMOS memory for cache systems which includes 49K bits SRAM and about 3500 transistors for logic will be presented. The memory achieves access times of 19ns from address to hit and 9.5ns from tag to hit, using address transition detection.

A sub-100 ns 256K DRAM with open bit line scheme

A 256K DRAM with a 34.1 mm/SUP 2/ die size and a typical access time of 70 ns has been fabricated by using a newly designed boosted high-level clock generator circuit and triple poly-Si processing. For two-cell array configurations and sensing schemes, the available signal and uncommon mode noise levels at the input terminal of the sense amplifiers were studied. It was concluded that the open bit line configuration was the better one for a high-speed 256 kbit DRAM with a small die size, and the device characteristics obtained confirmed this approach. The device can operate in the nibble mode with a 15-ns access time from a CAS clock and can be refreshed with CAS before RAS automatic refresh mode. The yield has been enhanced with optimized redundancy.

A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.<<ETX>>

A 70ns 4Mb DRAM in a 300mil DIP using 4-layer poly

divided into four 1Mb blocks which have its own clock drivers. Because only one of them operates in each read or write cycle, the RAM dissipates less than 40mA (typical). Each lhlb block has two arrays of column decoders with sense amplifiers on both sides of them. Figure 2 shows sense amplifier circuit. Isolation transistors are inserted between bitlines and an N-channel sense amplifier to isolate noises from the bit lines and to amplify a minute signal correctly. P-channel cross-coupled transistors are arranged outside the isolation transistors to restore a bit line and a cell to full VCC level.