Klaus Herold

Calibration of OPC models for multiple focus conditions

Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.

Etch aware optical proximity correction: a first step toward integrated pattern engineering

We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch. As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC. Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer. We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC has been applied and compare these results with conventional resist based OPC schemes. Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored. We present a process optimization flow that incorporates model based retargeting into resolution enhancement technology selection, materials selection as well as lithographic and reactive ion etch process development.

Managing high-accuracy and fast convergence in OPC

The transition to the 65nm technology node requires improved methodologies for model based optical proximity correction. The approaches used for previous generations might not be able to deliver the high accuracy which is necessary for gate patterning on high performance or low leakage circuits. A new categorization scheme for OPC fragments will be introduced, which then allows independent optimization for various OPC tool parameters. The feasibility of this technique will be demonstrated by quantifying the OPC convergence through iterations, which emphasizes the performance gain in OPC accuracy and runtime.

Double exposure double etch for dense SRAM: a designer's dream

As SRAM arrays become lithographically more aggressive than random logic, they are more and more determining the lithography processes used. High yielding, low leakage, dense SRAM cells demand fairly aggressive lithographic process conditions. This leads to a borderline process window for logic devices. The tradeoff obtained between process window optimization for random logic gates and dense SRAM is not always straightforward, and sometimes necessitates design rule and layout modifications. By delinking patterning of the logic devices from SRAM, one can optimize the patterning processes for these devices independently. This can be achieved by a special double patterning technique that employs a combination of double exposure and double etch (DE2). In this paper we show how a DE2 patterning process can be employed to pattern dense SRAM cells in the 45nm node on fully integrated wafers, with more than adequate overlap of gate line-end onto active area. We have demonstrated that this process has adequate process window for sustainable manufacturing. For comparison purpose we also demonstrate a single exposure single etch solution to treat such dense SRAM cells. In 45nm node, the dense SRAM cell can also be printed with adequate tolerances and process window with single expose (SE) with optimized OPC. This is confirmed by electrical results on wafer. We conclude that DE2 offers an attractive alternative solution to pattern dense SRAM in 45nm and show such a scheme can be extended to 32nm and beyond. Employing DE2 lets designers migrate to very small tip-to-tip distance in SRAM. The selection of DE2 or SE depends on layout, device performance requirements, integration schemes and cost of ownership.

Finding the right way: DFM versus area efficiency for 65 nm gate layer lithography

DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.

A new method for post-etch OPC modeling to compensate for underlayer effects from integrated wafers

In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers are not always accurate enough to deliver patterning solutions with stringent critical dimension requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for topography, differential etch due to different underlayer substrate based on local geometry and local loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data from two different OPC model versions built from flopdown and integrated wafer. We will also discuss modeling options in terms of two layer test masks for future technologies.

Single exposure is still alive: gate patterning at 45nm technology node

A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm technology node. They consist mainly of the introduction of a new software for optical proximity correction, the introduction of model based process window correction, the switch to model based etch proximity correction, and support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.

The comparison of OPC performance and run time for dense versus sparse solutions

The lithographic processes and resolution enhancement techniques (RET) needed to achieve pattern fidelity are becoming more complicated as the required critical dimensions (CDs) shrink. For technology nodes with smaller devices and tolerances, more complex models and proximity corrections are needed and these significantly increase the computational requirements. New simulation techniques are required to address these computational challenges. The new simulation technique we focus on in this work is dense optical proximity correction (OPC). Sparse OPC tools typically require a laborious, manual and time consuming OPC optimization approach. In contrast, dense OPC uses pixel-based simulation that does not need as much manual setup. Dense OPC was introduced because sparse simulation methodology causes run times to explode as the pattern density increases, since the number of simulation sites in a given optical radius increases. In this work, we completed a comparison of the OPC modeling performance and run time for the dense and the sparse solutions. The analysis found the computational run time to be highly design dependant. The result should lead to the improvement of the quality and performance of the OPC solution and shed light on the pros and cons of using dense versus sparse solution. This will help OPC engineers to decide which solution to apply to their particular situation.