Sajan Marokkey

3D physical modeling for patterning process development

In this paper we will demonstrate how a 3D physical patterning model can act as a forensic tool for OPC and ground-rule development. We discuss examples where the 2D modeling shows no issues in printing gate lines but 3D modeling shows severe resist loss in the middle. In absence of corrective measure, there is a high likelihood of line discontinuity post etch. Such early insight into process limitations of prospective ground rules can be invaluable for early technology development. We will also demonstrate how the root cause of broken poly-line after etch could be traced to resist necking in the region of STI step with the help of 3D models. We discuss different cases of metal and contact layouts where 3D modeling gives an early insight in to technology limitations. In addition such a 3D physical model could be used for early resist evaluation and selection for required ground-rule challenges, which can substantially reduce the cycle time for process development.

Three-dimensional physical photoresist model calibration and profile-based pattern verification

In this paper, we report large scale three-dimensional photoresist model calibration and validation results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although methods for calibrating physical photoresist models have been reported previously, we are unaware of any that leverage data sets typically used for building empirical mask shape correction models. . A method to calibrate and verify physical resist models that uses contour model calibration data sets in conjuction with scanning electron microscope profiles and atomic force microscope profiles is discussed. In addition, we explore ways in which three-dimensional physical resist models can be used to complement and extend pattern hot-spot detection in a mask shape validation flow.

Physical resist model calibration for implant level using laser-written photomasks

To reduce cost, implant levels usually use masks fabricated with older generation mask tools, such as laser writers, which are known to introduce significant mask errors. In fact, for the same implant photolithography process, Optical Proximity Correction (OPC) models have to be developed separately for the negative and positive mask tones to account for the resulting differences from the mask making process. However, in order to calibrate a physical resist model, it is ideal to use single resist model to predict the resist performance under the two mask polarities. In this study, we show our attempt to de-convolute mask error from the Correct Positive (CP) and Correct Negative (CN) tone CD data collected from bare Si wafer and derive a single resist model. Moreover, we also present the predictability of this resist model over a patterned substrate by comparing simulated CD/profiles against wafer data of various features.

Electrical validation of through-process optical proximity correction verification limits

Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.

Computational enablement for designs with sub-20nm metal tip to tip using cut shapes from grapho-epitaxy directed self-assembly

This paper presents a design and technology co-optimization (DTCO) study of metal cut formation in the sub-20-nmregime. We propose to form the cuts by applying grapho-epitaxial directed self-assembly. The construction of a DTCO flow is explained and results of a process variation analysis are presented. We examined two different DSA models and evaluated their performance and speed tradeoff. The applicability of each model type in DTCO is discussed and categorized.

Electrical Validation of Through Process OPC Verification Limits

Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper. Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.

Validating optical proximity correction with models, masks, and wafers

Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC models are used to convert input design shapes into mask data that often deviate significantly from both the initial design and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections, and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model and this is done by invoking OPC verification programs. The verification models identify points of failure to specific criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results, there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level and through OPC verification method. For each test case, five points in the process window space are chosen to provide comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to measurable metrics and provide an improved understanding of OPC verification validity.