Koen Uyttenhove

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-/spl mu/m CMOS

The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm/sup 2/. The ADC is implemented in a 0.25-/spl mu/m pure digital CMOS technology.

A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction

In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converters design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.

A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter

A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 /spl mu/m CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.

Speed-Power-Accuracy Trade-off in High-Speed Analog-to-Digital Converters; Now and in the future..

High-speed analog-to-digital converters (ADC’ s) are an essential part in a signal processing system. Radar applications and hard disk drive read channels require very high conversion speeds and relatively low resolutions (6–8 bits) [1][4]. Since several ADC’s may be needed in a “system-on-chip”, the ADC should only consume a small fraction of the total power budget [15]. In this article, a fundamental trade-off between speed, power and accuracy for high-speed converters is shown. This trade-off only depends on the matching data of the used process. Technology-scaling issues influencing this trade-off will be discussed. An important factor is the supply voltage; the never-ending story of technology trends towards smaller transistor dimensions has resulted to date in deep sub-micron transistors. The consequence is the downscaling of the power supply voltages, to date even lower than 2V, with almost the same threshold voltages of the CMOS transistors (in order to keep the leakage current in digital circuits small enough). This voltage scaling will have an impact on the previous mentioned trade-off between speed, power and accuracy. In the first section, high-speed ADC’s architectures are presented.

A CMOS 6-bit, 1 GHz ADC for IF sampling applications

The design plan and measurement results of a very high speed 6-bit CMOS Flash Analog-to-digital converter (ADC) are presented. The very high acquisition speed is obtained by improved comparator design and optimized pre-amplifier design. At these high frequencies power-efficient error correction logic is necessary. Measurements show the high conversion speed of the ADC. Maximum acquisition speed is above 1 GHz.

Speed-power-accuracy trade-off in high-speed ADCs: what about nano-electronics?

In this article the fundamental trade-off between speed, power and accuracy for high-speed converters is reviewed with respect to technology scaling. The never-ending story of technology trends towards smaller transistor dimensions has resulted to date in deep sub-micron transistors with lower supply voltages. It will be shown that in future technologies the power consumption of high-speed ADCs will increase to achieve the same accuracy and speed.

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter

The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converters specifications during high-level design and exploration. The inputs are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating A/D converter was developed for a WLAN application.

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter

The systematic design of a high-speed, high-accuracy Nyquist-rate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converters specifications during high-level design and exploration. The inputs to the flow are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.

Low Voltage Analog Design

The current trend towards low-voltage, low-power design is mainly driven by two important aspects: the growing demand for long-life autonomous portable equipment (cellular phones, PDAs, etc.) and the technological limitations of high-performance VLSI systems (heat dissipation). These two forces are now combined as portable equipment grows to encompass high-throughput intensive products such as portable computers and cellular phones. The most efficient way to reduce the power consumption of digital circuits is to reduce the supply voltage since the average power consumption of CMOS digital circuits is proportional to the square of the supply voltage. The resulting performance loss can be overcome for standard CMOS technologies by introducing more parallelism and/or modifying the process and optimizing it for low-voltage operation. The rules for analog circuits are quite different than those applied to digital circuits. It will be shown that the downscaling of the supply voltage does not automatically decrease the analog power consumption. After a general introduction on the limits to low power for analog circuits, an extensive part of this chapter will deal with the impact of reduced supply voltage on the power consumption of high-speed analog to digital converters (ADC). It will be shown that power consumption will not decrease and, even worse, will increase in future submicron technologies. This trend will be shown and solutions will be offered at the end of this chapter. A comparison with the power consumption of published high-speed analog to digital converters will also be presented.