Erik Lauwers

A CMOS multi-parameter biochemical microsensor with temperature control and signal interfacing

A fully-integrated microsensor chip allows continuous monitoring of concentrations of blood gases (pH, pO/sub 2/, pCO/sub 2/), ions, and biomolecules, and a conductometric measurement. The chip monitors 7 different chemical properties and includes temperature control and an EPROM. It occupies 25.7 mm/sup 2/ in a standard 1.2 /spl mu/m CMOS process including chemical sensor postprocessing and operates at 5 V.

Power estimation methods for analog circuits for architectural exploration of integrated systems

This paper describes methods for analog-power estimation and applies them practically to two different classes of analog circuits. Such power estimators, which return a power estimate given only a blocks specification values without knowing its detailed circuit implementation, are valuable components for architectural exploration tools and hence interesting for high-level system designers. As an illustration, two estimators are presented: one for high-speed analog-to-digital converters (ADCs) and one for analog-continuous time filters. The ADC power estimator is a technology scalable closed formula and yields first-order results within an accuracy factor of about 2.2 for the whole class of high-speed Nyquist-rate ADCs. The filter-power estimator is of a more complex nature. It uses a crude filter synthesis, in combination with operational transconductor amplifier behavioral models to generate accurate results as well, but restricted to certain filter implementations.

Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter

The design issues and tradeoffs of a high-speed high-accuracy Nyquist-rate analog-to-digital (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converters design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-/spl mu/m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.

A power estimation model for high-speed CMOS A/D converters

Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits information from reported designs is presented. The estimator is an analytical expression which is independent of the actual topology used and can easily be updated with new published designs. Experimental results show a good predictor accuracy of better than a factor 2.2 for most designs.

A 8-bit 200 MS/s interpolating/averaging CMOS A/D converter

A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 /spl mu/m CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.

ACTIF: a high-level power estimation tool for analog continuous-time filters

A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic range and signal swing. When used in combination with estimators for other building blocks (ADCs, DACs, mixers, ...) a truly high-level analog system exploration becomes feasible such as needed for architectural exploration of telecom systems. In literature only fundamental relations exist for analog filters, that predict the power with an error of orders of magnitude, which makes them hard to use in real system design. ACTIF combines existing filter synthesis methods with new behavioral models for transconductance stages in a novel way to obtain an optimized high-level yet accurate power estimation. To verify the presented approach, two recently published design examples are compared with the results from ACTIF.

High-level simulation and power modelling of mixed-signal front-ends for digital telecommunications

In this paper a methodology is described for architectural exploration of mixed-signal front-ends of transceivers for digital telecommunications. The methodology couples high-level simulations with high-level power estimators. In this way, both the performance (e.g. signal-to-noise-ratio) and the power consumption can be estimated at a high level, prior to implementation. The approach is illustrated with an architectural study of front-ends for upstream CATV modems.

Evaluation of the substrate noise effect on analog circuits in mixed-signal designs

This paper describes an approach used to simulate the bulk in such a way that we can evaluate the substrate noise effect on analog designs. For these simulations a simple model is used in order to reduce the time needed for the simulations. In this model we take into account the effect of the bonding wire and the bulk resistance. This simulation technique was applied to a sample and hold circuit.

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter

The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converters specifications during high-level design and exploration. The inputs are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating A/D converter was developed for a WLAN application.

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter

The systematic design of a high-speed, high-accuracy Nyquist-rate A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tools. A generic behavioral model is used to explore the A/D converters specifications during high-level design and exploration. The inputs to the flow are the specifications of the A/D converter and the technology process. The result is a generated layout and the corresponding extracted behavioral model. The approach has been applied to a real-life test case, where a Nyquist-rate 8-bit 200 MS/s 4-2 interpolating/averaging A/D converter was developed for a WLAN application.