Koen Verhaege

Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides

A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. f/sub Tmax/=45 GHz in BiCMOS-0.35 /spl mu/m LNA input) and thin gate-oxides (e.g. tox=1.7 nm in CMOS-0.09 /spl mu/m input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBTs.

Influence of tester, test method, and device type on CDM ESD testing

In this paper, the charged device model (CDM) electrostatic discharge (ESD) events emulated by different commercial concerns are studied. First, the characteristic waveforms, defined by the EOS/ESD CDM ESD draft standard (DS5.3-1993), are compared and some major problems related to the specification of socketed CDM testers are discussed. Second, the results of an extensive CDM ESD test program are reported. The influences of various test parameters, such as the charging method (direct or field), the discharge mode (contact or noncontact), the charge pin (substrate pin or pin to be discharged) and the device package are studied. Finally, correlations of CDM ESD test results (the voltage thresholds and electrical failure signatures) are investigated. >

Double snapback in SOI nMOSFETs and its application for SOI ESD protection

Double snapback in silicon-on-insulator (SOI) nMOSFETs is reported. An extensive experimental analysis of this phenomenon and a tentative model are presented. It is shown that this double-snapback phenomenon offers a basis for an electrostatic discharge (ESD) protection concept for SOI technologies.<<ETX>>

TLP calibration, correlation, standards, and new techniques [ESD test]

This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at TLP data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.

Grounded-gate nMOS transistor behavior under CDM ESD stress conditions

This paper contains a systematic study into the effects of design and process variations on the behavior of the grounded-gate nMOS transistor under CDM ESD stress conditions. The correlation of both electrical behavior and physical failure is evaluated for socketed CDM, nonsocketed CDM, and HBM ESD stress models. It is shown that a new compact transistor model, concerning its application for the simulation of CDM behavior, is employed in electro-thermal simulation to explain the experimental results.

High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation ☆

This paper presents a novel SCR for power line and local I/O ESD protection. The HHI-SCR exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current is controlled by device design. The HHI-SCR is demonstrated in 0.10um-CMOS and in a 0.4um-BiCMOS technology. The design is highly area efficient.

Investigation into socketed CDM (SDM) tester parasitics

The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly affects the SDM failure threshold voltage levels and may lead to miscorrelation and nonreproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides 10 to 20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.

The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's

The objective of this paper is to discuss the characteristics of SOI1 nMOSFETs that can be exploited to clamp HBM(2) ESD(3) stresses and to explain the related failure modes and mechanism observed in these devices. The influence on the HBM ESD protection capability of the first order main parameter: the nMOSFET gate length is investigated. The ESD protection capability for both positive and negative polarity HBM stresses is elaborated and compared. The ESD clamping and device failure mechanisms limiting the ESD protection performance are identified.