Takeshi Okazawa

A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far.<<ETX>>

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain size must be shrunk proportional to the cell size. A process technology breakthrough will have to be achieved to form smaller size grains because 16 M will be the maximum capacity using current process technology with this new theory. It is also shown how 64 M flash memories can be achieved without such a technology breakthrough.<<ETX>>

A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory

A 0.4- mu m stacked gate cell for a 64-Mb flash memory has been developed which has the symmetrical side wall diffusion self-aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p/sup +/ pockets at both the drain and the source, an adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the uniform erasing scheme applying negative bias to the gate which is adopted for the SSW-DSA cell shows lower trapped charges after write/erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance and retention characteristics than nonuniform erasing schemes. This cell will enable the realization of a 64-Mb flash memory with single 5-V supply operation, 10/sup 6/ W/E endurance, and sector erasing scheme.<<ETX>>

A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme

A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This memory is fabricated using a 0.4 /spl mu/m-design-rule, double-layer-aluminum, triple-layer-polysilicon, twin-well CMOS technology. To reduce operating voltage, a high-capacitive-coupling ratio (HiCR) cell with high coupling ratio between the control gate and the floating gate is used.<<ETX>>

A 0.1- mu A standby current, ground-bounce-immune 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM (SRAM) that has very high immunity against ground bounce has been developed. The novel circuit techniques of the multiple clock generator configuration and the optimization of the transient response characteristics of the clock generators have been developed for the ground-bounce immunity. A thin-film transistor has been used as a memory cell load device instead of the conventional polysilicon resistor. The access time of the SRAM is 35 ns and the standby current is 0.1 mu A. The memory cell size is 41.08 mu m/sup 2/. >

A 0.54 /spl mu/m/sup 2/ self-aligned, HSG floating gate cell (SAHF cell) for 256 Mbit flash memories

A 0.54 /spl mu/m/sup 2/ self-aligned memory cell with hemispherical-grained (HSG) poly-Si floating gate (SAHF cell) has been developed for 256 Mbit flash memories. Applying hemispherical-grained (HSG) poly-Si to floating gate extends the upper surface area to double that of the floating gate in comparison with the conventional ones. A high capacitive-coupling ratio of 0.8 and buried n/sup +/ diffusion layers which are self-aligned to the floating gate poly-Si are realized simultaneously with a simple cell structure and fewer process steps.

A 3.6 mu m/sup 2/ memory cell structure for 16 Mb EPROMs

A 2.0- mu m*1.8- mu m floating-gate-type memory cell, based on a 0.6- mu m design rule, has been developed for 16-Mb EPROMs (electrically programmable ROMs). The cell size is about 40% that of the smallest 4-Mb EPROM cell reported so far. The cell also features a fast programming time of 10 mu s. The process technologies used are trench-self-aligned isolation refilled with BPSG, oxide-nitride-oxide interpoly dielectrics and bit-line contact with silicide pad and selective CVD (chemical vapor deposited) tungsten.<<ETX>>

A high speed signal processor by the device scaling

Operation speed improvement of a digital signal processor of N-channel enhancement/ depletion circuit type, has been realized by the application of the device scaling technology. The original version of the signal processor with 3.1 micron design rule has been scaled down simply into the two versions with 2.5 and 2.0 micron design rules. With this scaling down, the operation clock frequency, 11 MHz in original version, has been improved to 18 MHz and 21 MHz, respectively. From this investigation, an experimental relation that the power-delay product of a microprocessor is almost proportional to the 1.5-th power of the scaling factor has been derived in association with the similar experiments on other CPUs, instead of the third power law predicted from the simple theory.