Noriaki Kodama

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

Clear evidence is presented that the floating gate poly-Si grain size dominates flash memory erase characteristics. Smaller grain size shows a narrower erase distribution. Thus conventional scaling theories should be modified to include that grain size must be shrunk proportional to the cell size. A process technology breakthrough will have to be achieved to form smaller size grains because 16 M will be the maximum capacity using current process technology with this new theory. It is also shown how 64 M flash memories can be achieved without such a technology breakthrough.<<ETX>>

A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory

A 0.4- mu m stacked gate cell for a 64-Mb flash memory has been developed which has the symmetrical side wall diffusion self-aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p/sup +/ pockets at both the drain and the source, an adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the uniform erasing scheme applying negative bias to the gate which is adopted for the SSW-DSA cell shows lower trapped charges after write/erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance and retention characteristics than nonuniform erasing schemes. This cell will enable the realization of a 64-Mb flash memory with single 5-V supply operation, 10/sup 6/ W/E endurance, and sector erasing scheme.<<ETX>>

Impact of mechanical stress on interface trap generation in Flash EEPROMs

We show that the compressive mechanical stress in the channel of a Flash EEPROM cell degrades data retention characteristics through the generation and recovery of traps at the tunnel-oxide/Si substrate interface. To demonstrate this, we measured the mechanical stress and interface trap density in 0.15 /spl mu/m-rule NOR cells using convergent-beam electron diffraction and charge pumping methods. Hydrogen atoms, another possible factor, had less influence than mechanical stress.

A 0.1- mu A standby current, ground-bounce-immune 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM (SRAM) that has very high immunity against ground bounce has been developed. The novel circuit techniques of the multiple clock generator configuration and the optimization of the transient response characteristics of the clock generators have been developed for the ground-bounce immunity. A thin-film transistor has been used as a memory cell load device instead of the conventional polysilicon resistor. The access time of the SRAM is 35 ns and the standby current is 0.1 mu A. The memory cell size is 41.08 mu m/sup 2/. >

A 3.6 mu m/sup 2/ memory cell structure for 16 Mb EPROMs

A 2.0- mu m*1.8- mu m floating-gate-type memory cell, based on a 0.6- mu m design rule, has been developed for 16-Mb EPROMs (electrically programmable ROMs). The cell size is about 40% that of the smallest 4-Mb EPROM cell reported so far. The cell also features a fast programming time of 10 mu s. The process technologies used are trench-self-aligned isolation refilled with BPSG, oxide-nitride-oxide interpoly dielectrics and bit-line contact with silicide pad and selective CVD (chemical vapor deposited) tungsten.<<ETX>>