Koichi Kanzaki

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >

DLTS Study of RIE-Induced Deep Levels in Si Using p^+n Diode Arrays

Deep levels in Si induced by reactive ion etching (RIE) of SiO2 film have been studied by DLTS. In order to detect the RIE-induced damage existing near the surface region, special device structures consisting of p+n diode arrays are used. It is found that the dominant deep levels produced by RIE are four hole traps. One level at Ev+0.40 eV exhibits the Poole-Frenkel effect, from which it is identified as an acceptor. Another level at Ev+0.46 eV is deduced to be an interstitial iron level from the emission rate. There is a strong decrease in the deep level concentrations upon annealing above 500°C. However, the deep levels do not completely disappear upon annealing at high temperatures. The deep level concentrations correlate well with the current-voltage characteristics of the devices.

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

The long-term reliability for a p/sup +/ poly gate MOS structure under low electric field bias temperature (BT) stress is studied. A significant increase in interface-state density was observed for such a structure under positive bias conditions. This phenomenon was not observed in the n/sup +/ poly gate case. The mechanism for this interface-state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and hole injection from the gate electrode, were considered. All of the possible causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p/sup +/ poly gate is a possible cause, which could explain the interface-state generation under positive-bias temperature test. For a p/sup +/ poly gate in CMOS structures, care should be taken when positive bias is applied to the gate electrode. >

Electromigration reliability for a tungsten-filled via hole structure

Experiments have shown that the electromigration reliability for conventional nonfilled via holes decreases with via hole diameter reduction. Tungsten-filled via hole reliability, however, is independent of the via hole diameter and improves significantly compared with the nonfilled via hole structure. The electromigration failure mechanism for the tungsten-filled via hole structures was investigated by two-dimensional numerical simulation. Current crowding points were found near the via hole edge in the aluminum part. Via hole resistance change during the electromigration test was also evaluated. When aluminum-silicon was used for the metal lines, via hole resistance increased, due to the migration of silicon in the aluminum line. However, it was estimated as being negligibly small for unusual operating conditions. >

Mechanism of hot electron induced degradation in LDD NMOS-FET

The hot electron induced degradation of the N-channel LDD MOS-FETs was studied and compared with the conventional one. The LDD NMOS-FET has its own degradation mode, the decrease of the trans-conductance and the drain current. This mechanism of the degradation was clarified by the reliability tests and the 2-dimensional device simulation considering the drift of the injected electrons in the gate oxide. Most of the generated surface states were localized near the drain edge and modulate the parasitic drain resistance of the LDD NMOS-FET, but do not affect the conventional one.

Resistance modulation effect in n-well CMOS

The characteristics of n-well CMOS latchup have been measured and quantitatively analyzed. It was found that the resistance of the substrate and of the well modulated by minority-carrier injection from the emitter of the parasitic bipolar transistors, and that the latchup trigger current was about two times larger than that calculated without the modulation. It was also confirmed that the holding current level is well explained if the modulation effect is brought into consideration. The latchup analysis with the modulation effects should give useful information for optimizing the structure and concentration of the well and the substrate.

Properties of InSb Photodiodes Fabricated by Liquid Phase Epitaxy

High detectivity InSb photodiodes have been developed by using the liquid phase epitaxy technique. They have n on p structure. Infrared radiation absorption in the Te doped n layer is quite small, due to the Burstein-Moss effect. The quantum efficiency of the photodiode is limited only by diffusion length Ln of minority carriers in the p region. Values obtained were from 0.2 to 0.3. The zero bias resistance of 2 mm diodes was from 100 to 200 kΩ. Specific detectivity Dλ*(λ=5 µm, frequency 1 kHz) was from 5×1010 to 1×1011 cmHz1/2/W.

17.1: Invited Paper: Direction of Low‐Temperature p‐Si Technology

Low temperature p-Si technology road map is proposed and discussed focusing on the evollution of TFT performance and integration density. Integration of DAC and control circuits will realize lighter-weight and lower cost display, where, higher resolution and larger display size require higher TFT performance. While, higher integration density enables multi-bits(∼ 8bits) memories in pixels and significantly reduces the driving power consumption. Another key is the combination of OLED, which will replace LCD and become the main stream flat panel technology.

Propagation delay time dependence on gate geometry for the self-aligned I 2 L

The gate geometry dependence of the minimum pro.- pagation delay time (t<inf>pdm</inf>) was investigated for the self-aligned I²L. Switching characteristics were measured by using I²L test patterns with different base contact geometries and collector widths (W<inf>c</inf>); t<inf>pdm</inf>=0.9 nS for a double base contact and W<inf>c</inf>= 4µm I²L gate and f<inf>toggle-max</inf>= 150 MHz for a divide-by two circuit with W<inf>c</inf>= 7 µm I²L gates. Experimental results suggest that the resistance of the intrinsic base area for the n-p-n transistor has strong influence on t<inf>pdm</inf>. An analysis based on a charge control model which includes this base resistance effect was carried out and the experimental results were explained very well.

+ BT Instability in P + poly gate MOS structure

Long term reliability of p+poly gate MOS structure with thin gate oxide was investigated and compared with n+poly gate. Instability in positive low bias temperature (-BT) stress was found out in p+poly gate. Increase of interface states and negative flat band voltage shift were observed after +BT stress test. Increase of interface states does not depend on boron dose into the poly Si gate and phosphorus gettring process, and no interface state generation appears in n+poly gate containing implanted borons. So, the mobile ions and borons are not origin of the interface state generation. Therefore, the only one mechanism, which is not denied, is that holes are injected from p+poly gate into the oxide and generate interface states.