Y. Niitsu

Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5- mu m Bi-CMOS process

A low-temperature-processed (800-850 degrees C) bipolar transistor design suitable for the high-performance 0.5- mu m BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar transistor design in the high-performance 0. 5- mu m Bi-CMOS process are proposed. The As-P emitter and selectively implanted collector structures, annealed using RTA, were found to be suitable for the advanced Bi-CMOS process. >

Latchup-free CMOS structure using shallow trench isolation

Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and the epitaxial layer thickness is 2 µm, the latchup holding voltage, VHis higher than 13 V. The mechanism of VHincrease is discussed using an equivalent circuit including the reverse transistors of the parasitic bipolar transistors. The interruption of lateral current flow with the trench contributes to VHincrease. From the results, it is well expected that the only about 1 µm deep trench must be adequate for achieving VHhigher than the supply voltage, i.e. 5V, and that the fabrication process of trench isolation becomes more reliable and easier.

0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

A channelless gate array has been realized using 0.5- mu m BiCMOS technology integrating more than two million transistors on a 14-mm*14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell. >

Resistance modulation effect in n-well CMOS

The characteristics of n-well CMOS latchup have been measured and quantitatively analyzed. It was found that the resistance of the substrate and of the well modulated by minority-carrier injection from the emitter of the parasitic bipolar transistors, and that the latchup trigger current was about two times larger than that calculated without the modulation. It was also confirmed that the holding current level is well explained if the modulation effect is brought into consideration. The latchup analysis with the modulation effects should give useful information for optimizing the structure and concentration of the well and the substrate.

Bipolar transistor design for low process-temperature 0.5 mu m Bi-CMOS

A low-temperature (800-850 degrees C) processes bipolar transistor design suitable for high-performance 0.5- mu m BiCMOS process is discussed. It was found that insufficient activation of arsenic in the emitter, fast base boron diffusion in the low-concentration region caused by implantation damages for the direct-ion-implanted emitter case, and insufficient arsenic diffusion from the poly-Si for the poly-Si emitter case should be considered as serious problems when the low-temperature furnace anneal is used. High-temperature RTA (rapid thermal annealing) is shown to solve those problems. Based on the impurity diffusion behaviors and related electric bipolar characteristics, the optimum conditions and structures for bipolar transistor design for the high-performance 0.5- mu m BiCMOS process are discussed.<<ETX>>

A 350 ps 50 K 0.8 amu;m BiCMOS gate array with shared bipolar cell structure

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8- mu m BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of the element switch architecture are CASO buffers to increase the throughput, a synchronization technique called SCDB (synchronization in a clocked dual port buffer) to make possible asynchronous cell transmission on the element switches with simple hardware, and an implementation technique for virtual cut through, called CELL-BYPASS, which lowers the latency. An implementation of elastic store is proposed to achieve high-speed synchronization with simple hardware. The element switch LSI adopts an emitter-coupled-logic (ECL) interface. The maximum operation frequency of the element switch LSI is 200 MHz (typical). >

A 3.3 V, 0.5 mu m BiCMOS technology for BiNMOS and ECL gates

A 0.5- mu m BiCMOS technology for achieving speed performance with scaling is described. For the lower supply voltage of 3.3 V, the delay time of the conventional BiCMOS gate becomes almost equal to that of the CMOS gate. A BiNMOS circuit was employed and achieved a speed advantage over the CMOS at 3.3 V. To improve bipolar performance and its ECL (emitter coupled logic) gate delay time, a selectively ion-implanted collector technology, was investigated and a quasi-self-aligned bipolar transistor with double polysilicon layers was utilized. The ECL gave achieved a delay time of 57 ps/stage. Both gates retained the speed performance for the scaling trend.<<ETX>>

Comparison between poly emitter bipolar characteristics with and without native oxide layers under various processes

The effect of the interfacial native oxide layer between polycrystalline and single-crystal Si was investigated in the submicron-rule bipolar and BiCMOS processes. It was found that the native oxide increases the current gain, but significantly degrades bipolar transistor performance. Bipolar transistors without the oxide layer, fabricated by different methods, were investigated. Without the layer, low emitter resistance and small current gain variation were achieved for a low-temperature process. The current gain reduction due to the lack of the oxide layer does not degrade the cutoff frequency. Improved performance for structures without native oxide was confirmed with ECL (emitter-coupled logic) ring oscillators.<<ETX>>

0.5 mu m BiCMOS standard-cell macros including 0.5 W 3 ns register file and 0.6 W 5 ns 32 kB cache

BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5- mu m BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.<<ETX>>