Koichi Takeuchi

Influence of underlayer reflection on optical proximity effects in sub-quarter-micron lithography

The relationship between the optical proximity effect (OPE) and the underlayer reflection has been investigated by using negative and positive resists in sub-quarter-micrometer lithography. A new evaluation method that uses the center exposure dose of the ED-window (1-2) is been proposed. This technique takes the manufacturing margin into consideration and can be used to obtain the common ED-window of isolated and density patterns. The negative resists show a small critical dimension variation between isolated and density lines (CD bias) with the most suitable exposure dose and best focus conditions. However, the common ED-window of the isolated and density patterns is poor in terms of the manufacturing margin. Furthermore, the (sigma) dependence of the negative resist is too weak to improve the manufacturing margin. The effect of the underlayer reflection on the CD bias of the negative resist is significant in our experiment. On the other hand, the positive resist shows strong (sigma) dependence. Because the influence of the underlayer reflection on the positive resist is small, it is important to optimize (sigma) when improving the CD bias for the positive resist. In order to compare the negative and positive resists under equivalent conditions, a resist development simulation was used. The simulation results show the negative resist could be capable of high performance.

Lithography of choice for the 45-nm node: new medium, new wavelength, or new beam?

In order to clarify the direction of the lithography for the 45 nm node, the feasibilities of various lithographic techniques for gate, metal, and contact layers are studied by using experimental data and aerial image simulations. The focus and exposure budget have been determined from the actual data and the realistic estimation such as the focus distributions across a wafer measured by the phase shift focus monitor (PSFM), the focus and exposure reproducibility of the latest exposure tools, and the anticipated 45 nm device topography, etc. 193 nm lithography with a numerical aperture (NA) of 0.93 achieves the half pitch of 70 nm (hp70) by using an attenuated phase shift mask (att-PSM) and annular illumination. 193 nm immersion lithography has the possibility to achieve the hp60 without an alternative PSM (alt-PSM). For a gate layer, 50-nm/130-nm line-and-space (L/S) patterns as well as 50 nm isolated lines can be fabricated by an alt-PSM. Although specific aberrations degrade the critical dimension (CD) variation of an alt-PSM, ±2.6 nm CD uniformity (CDU) is demonstrated by choosing the well-controlled projection lens and using a high flatness wafer. For a contact layers, printing 90 nm contacts is very critical by optical lithography even if the aggressive resolution enhancement technique (RET) is used. Especially for dense contact, the mask error factor (MEF) increases to around 10 and practical process margin is not available at all. On the other hand, low-energy electron-beam proximity-projection lithography (LEEPL) can fabricate 80 nm contact with large process margin. As a lithography tool for the contact layers of the 45 nm node devices, LEEPL is expected to replace 193 nm lithography.

Challenges to depth-of-focus enhancement with a practical super-resolution technique

A new technique, which combines weak quadrupole illumination and an attenuated phase- shifting mask, has been developed. 0.03 micrometers lithography with i-line can be performed with this technique. It is also confirmed that KrF excimer laser lithography is a powerful candidate for generating 0.18 micrometers -rule devices.

Recording Video Camera in the Beta Format

In this paper we shall introduce the small diameter head drum VCR System that uses exactly the same recording format as the original large diameter head drum system. Having identified the different factors of the tape pattern with the mechanical parts, we were able to develop a new technique of recording the same information as is done in the original format. As this is specialized for only recording, we were able to drastically reduce the number of both the mechanical parts and circuits in our compact all-in-one camera/VCR.

Extension of krypton fluoride excimer laser lithography to the fabrication of 0.18 μm devices

This article presents the extension of krypton fluoride (KrF) excimer laser lithography. An 0.18 μm device can be fabricated by KrF excimer laser lithography when weak off-axis illumination is combined with an attenuated phase-shifting mask, a high-performance antireflective layer, and a high-numeral-aperture exposure tool. A 1.0 μm depth-of-focus can be achieved for 0.18 μm rule logic patterns. The weak off-axis illumination can reduce the influences of the secondary peak in the high-duty periodic patterns, and retain the depth-of-focus for isolated patterns when it is used in combination with an attenuated phase-shifting mask. A high-performance antireflective layer can increase the depth-of-focus because a uniformly exposed area in the photoresist can be formed when the light reflected from the substrate is eliminated.

A novel robust optimization method of exposure and mask conditions for beyond 65 nm-node lithography

Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of control and error factors has been increasing. This holds especially true for alternating phase-shifting mask (alt-PSM) techniques; i.e., for this technique, not only exposure conditions but also mask structures should be optimized under various error factors (or noise factors), such as defocus, dose fluctuations, lens aberrations, mask making errors and so on. This paper describes a novel method of performing such optimization, which is developed based on a method of design of experiments (DOEs). Stabilities of target performance for various combinations of parameters are simulated by varying noise factor levels which are assigned to an orthogonal array. Optimum values of parameters are determined so as to maximize the stabilities of target performance. This method is applied to a 45-nm node alt-PSM (alternating phase-shifting mask) technique. Optical conditions, such as NA (numerical aperture) and σ-value, and mask structures, such as trench depth and undercut size, are optimized under various noise factors by applying our method for optimization. As a result, high stability of critical dimension (CD) is obtained together with sufficient suppression of image placement errors. The optimized result is further verified by statistic calculations. Finally, we conclude that our method is a very powerful tool to simultaneously optimize lithographic conditions for low-k1 lithography processes.

Novel robust optimization method of lithographic conditions for correlative multilayers beyond 65 nm node

Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of error factors and that of critical patterns have been increasing. In order to attain a target performance of integrated circuits under numerous error factors (or noise factors), this paper describes a novel method to optimize various parameters simultaneously. The parameters include not only those related to exposure conditions such as NA, sigma and etc, but also include those related to layout restrictions for various patterns. The optimization method we applied is based on the Taguchi method for robust design experiments, which uses orthogonal arrays with a single criterion, which is called “signal-to-noise (SN) ratio”, for optimization. The optimization is performed so as to maximize the SN ratio for a pattern critical-dimension (CD) or the SN ratio for an operating window such as the open-to-short operating window of electric connections. Two cases of optimization are reported in this article, one for an intermediate metal layer in a 45 nm-node device, and the other for a via-hole layer connected to the metal layer. Any type of noise factors and critical patterns could be taken into account and an optimum set of parameters could be determined quickly and simultaneously by applying the method. The results demonstrate that this global optimization method is a very powerful tool to optimize multiple parameters in low-k1 lithography processes.

ArF lithography technologies for 65 nm-node CMOS (CMOS5) with 30 nm logic gate and high density embedded memories

In this paper ArF lithography technology for 65nm-node CMOS with 30nm logic gate and high density embedded memories have been demonstrated. ArF step-and-scan exposure systems with 0.75NA are available under accurate lithography design with level specific focus and does error budgets. Also,the process steps with two kinds of lithography are implemented to fabricate GC pattern.