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Dive into the research topics where Koji Sadamatsu is active.

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Featured researches published by Koji Sadamatsu.


Materials Science Forum | 2016

Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode

Shiro Hino; Hideyuki Hatta; Koji Sadamatsu; Yuichi Nagahisa; Shigehisa Yamamoto; Toshiaki Iwamatsu; Yasuki Yamamoto; Masayuki Imaizumi; Shuhei Nakata; Satoshi Yamakawa

External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.


international symposium on power semiconductor devices and ic's | 2017

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

Koutarou Kawahara; Shiro Hino; Koji Sadamatsu; Yukiyasu Nakao; Yusuke Yamashiro; Yasuki Yamamoto; Toshiaki Iwamatsu; Shuhei Nakata; Shingo Tomohisa; Satoshi Yamakawa

For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.


Materials Science Forum | 2018

Investigation of the Robust Edge Termination Applied to 6.5kV SiC MOSFET

Kohei Ebihara; Koutarou Kawahara; Shiro Hino; Koji Sadamatsu; Akemi Nagae; Yukiyasu Nakao; Hiroshi Watanabe; Satoshi Yamakawa

High breakdown voltage and smaller size of edge termination are required in SiC power devices. We simulated reverse bias characteristics of a variety of edge terminations targeting 6.5 kV MOSFET and the FLR showed the best trade-off between the size and the implanted Al dose. Fabricated pn diode TEGs with a FLR demonstrated over 6.5 kV breakdown voltage. We observed the avalanche breakdown visually by light emission and it corresponded to the simulated electric field. These indicate that we can fabricate the desirable FLR for 6.5 kV MOSFET.


Materials Science Forum | 2018

Impact of Embedding Schottky Barrier Diodes into 3.3 kV and 6.5 kV SiC MOSFETs

Koutarou Kawahara; Shiro Hino; Koji Sadamatsu; Yukiyasu Nakao; Toshiaki Iwamatsu; Shuhei Nakata; Shingo Tomohisa; Satoshi Yamakawa

External Schottky barrier diodes (SBDs) used as free-wheel diodes should be larger in higher voltage devices to avoid bipolar degradation consequent on current conduction of body diodes in SiC MOSFETs. By embedding an external SBD into an SiC MOSFET, we achieved compact 3.3 kV and 6.5 kV SiC MOSFETs that are free from bipolar degradation. The active area of the 3.3 kV/6.5 kV samples is only about a half/quarter of the total active area of a conventional MOSFET and a coupled external SBD.


Materials Science Forum | 2018

Impact of Stripe Trench-Gate Structure for 4H-SiC Trench MOSFET with Bottom Oxide Protection Layer

Yutaka Fukui; Katsutoshi Sugawara; Kohei Adachi; Hideyuki Hatta; Kazuya Konishi; Koji Sadamatsu; Nobuo Fujiwara; Shingo Tomohisa; Satoshi Yamakawa

An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (dBPWs). For the stripe structure, more significant improvements on the specific on-resistance (Ron,sp), gate-source threshold voltage (Vth) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.


international symposium on power semiconductor devices and ic's | 2010

Advanced RFC technology with new cathode structure of field limiting rings for High Voltage planar diode

Katsumi Nakamura; Fumihito Masuoka; Akito Nishii; Koji Sadamatsu; Soichi Kitajima; Kazunari Hatade


international symposium on power semiconductor devices and ic's | 2010

Wide Cell Pitch LPT(II)-CSTBT™(III) technology rating up to 6500 V for low loss

Katsumi Nakamura; Koji Sadamatsu; Daisuke Oya; Hidenori Shigeoka; Kazunari Hatade


Archive | 2014

Verfahren zum Testen einer Halbleitervorrichtung

Eiko Otsuki; Yasuhiro Yoshiura; Koji Sadamatsu


Archive | 2014

METHOD OF TESTING SEMICONDUCTOR DEVICE

Eiko Otsuki; Yasuhiro Yoshiura; Koji Sadamatsu


Archive | 2014

Verfahren zum Testen einer Halbleitervorrichtung A method for testing a semiconductor device

Eiko Otsuki; Yasuhiro Yoshiura; Koji Sadamatsu

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