Yohei Morishita

A 60GHz wireless transceiver employing hybrid analog/digital beamforming with interference suppression for multiuser gigabit/s radio access

This paper presents a 60GHz analog/digital beamforming transceiver that effectively suppresses interference signals, targeting WiGig/IEEE 802.11ad standard. A prototype has been built with 40nm CMOS analog front-ends as well as offline baseband digital signal processing. Measurement shows 3.1dB EVM advantage over the conventional two-stream diversity during a packet collision situation.

A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad

A PVT tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad is presented. By introducing a newly proposed self-sensing LDO, the transceiver adjusts bias currents and the LDO output voltage for the PA to minimize the output power variation while relaxing the hot carrier injection (HCI) degradation. The measurement shows excellent robustness against PVT variations, demonstrating only 5 dB output power variation over -20 °C to 85 °C across process corners.

A Direct Sampling Mixer with complex coefficient transfer function in 65nm CMOS

The Direct Sampling Mixer (DSM) with complex coefficient transfer function is demonstrated. The operation theory and the detail design methodology are discussed for the 2-pararell architecture, which can achieve large image rejection by introducing the attenuation pole at the image frequency band. The proposed architecture was fabricated in a 65nm CMOS process. The measured results agree well with the theoretical calculation, which proves the validity of the proposed architecture and the design methodology. By using the proposed design method, it will be possible for circuit designers to design the DSM with large image rejection ratio without repeated lengthy simulations.

Nonlinear analysis of MOS FET passive mixers as a function of local signal

The linearity analysis of a passive mixer is presented. The distortion mechanism caused by switching operation of an NMOS transistor is elucidated from the DC analysis of passive mixers. Furthermore, the maximum input level to keep linear operation and its required bias condition is derived. The calculated linearity performances agree well with simulated results.

A 2.5 GHz programmable wideband low pass filter with a hybrid Continuous-Time/Discrete-Time equalizer in 40 nm CMOS

This paper presents a programmable wideband low pass filter (LPF) with a hybrid Continuous-Time (CT)/Discrete-Time (DT) equalizer. Unlike the conventional DT LPF design, the proposed LPF eliminates sample & hold circuits, enabling to achieve much wider bandwidth. The transfer function is derived from CT/DT hybrid analysis. A prototype has been fabricated in 40 nm CMOS. The proposed LPF achieves 2.5 GHz bandwidth by wideband equalization with capacitance ratio (C ratio) and clock frequency (ƒCK) programmability. The proposed LPF occupies 0.048 mm2 of active area.