Koon-Lun Jackie Wong

Offset compensation in comparators with minimum input-referred supply noise

The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

A low-power quarter-rate sampling 2-tap DFE is realized for short I/O links. An analog sampling and soft-decision technique is used instead of look-ahead architectures to relax the critical path, and thus saving the power from the redundant paths. No errors are observed with 231-1 PRBS at 6Gb/s, with 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3GHz. The receiver draws 4.8mA from a 1.0-V supply

A 10-mW 3.6-Gbps I/O transmitter

This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.

A 27-mW 3.6-Gb/s I/O transceiver

This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10-12 with 231-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply

A broadband 44-GHz frequency divider in 90-nm CMOS

The paper presents two designs of high-frequency, broadband frequency dividers. The designs are optimized for stability across process variations and high operating frequencies. The first design divides an input frequency range of 4-44GHz, drawing 4.4mA from a 1.2-V supply. The minimum input power is -5dBm at 40GHz. No performance degradation is observed at 50/spl deg/C, and only 16% degradation at 75 /spl deg/C. A second divider operates from dc-37GHz, consuming only 1.6mW at 30GHz. By not using inductive peaking, the designs achieve high bandwidth and small area (19/spl mu/m by 40/spl mu/m).

A Serial-Link Transceiver with Transition Equalization

Two transition-equalization techniques are proposed. A pulse-overlapping half-symbol tap FIR transmitter is able to equalize a 120-inch 40dB attenuation FR4 with BER of <10-13at 3.7Gb/s. A DFE with transition ISI cancellation performs better than traditional DFE and achieves a BER of <10-12at 3.6Gb/s with 80-inch FR4

Modified LMS Adaptation Algorithm for a Discrete-Time Edge Equalizer of Serial I/O

Discrete-time edge equalizers can enhance symbol-rate equalizers by compensating for inter-symbol interference at data transitions (timing ISI). The reduced timing ISI improves the timing margin and provides the CDR with clean timing information. This paper shows that adapting tap weights with standard blind LMS algorithm results in a reduced eye and may not converge. A modified algorithm is introduced to maximize the data eye.

Analysis of timing recovery for multi-Gbps PAM transceivers

The increasing data rates for many short distance (<1 m PCB) chip-to-chip links are exceeding the bandwidth limitation of the channel. With the sharp channel roll-off for many applications, pulse-amplitude modulation (PAM) has emerged as a means for improved channel efficiency. The modulation impacts both voltage and timing margins for the signal. Timing recovery in particular increases in complexity. This paper reviews various timing recovery methods for PAM signals and how the limited bandwidth affects the timing margin and timing recovery.