Kosuke Katayama

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels

The vast unallocated frequency band lying above 275GHz offers enormous potential for ultrahigh-speed wireless communication. An overall bandwidth that could be allocated for multi-channel communication can easily be several times the 60GHz unlicensed bandwidth of 9GHz. We present a 300GHz transmitter (TX) in 40nm CMOS, capable of 32-quadrature amplitude modulation (QAM) 17.5Gb/s/ch signal transmission. It can cover the frequency range from 275 to 305GHz with 6 channels as shown at the top of Fig. 20.1.1. Figure 20.1.1 also lists possible THz TX architectures, based on recently reported above-200GHz TXs. The choice of architecture depends very much on the transistor unity-power-gain frequency fmax. If the fmax is sufficiently higher than the carrier frequency, the ordinary power amplifier (PA)-last architecture (Fig. 20.1.1, top row of the table) is possible and preferable [1-3], although the presence of a PA is, of course, not a requirement [4,5]. If, on the other hand, the fmax is comparable to or lower than the carrier frequency as in our case, a PA-less architecture must be adopted. A typical such architecture is the frequency multiplier-last architecture (Fig. 20.1.1, middle row of the table). For example, a 260GHz quadrupler-last on-off keying (OOK) TX [6] and a 434GHz tripler-last amplitude-shift keying (ASK) TX [7] were reported. A drawback of this architecture is the inefficient bandwidth utilization due to signal bandwidth spreading. Another drawback is that the use of multibit digital modulation is very difficult, if not impossible. An exception to this is the combination of quadrature phase-shift keying (QPSK) and frequency tripling. When a QPSK-modulated intermediate frequency (IF) signal undergoes frequency tripling, the resulting signal constellation remains that of QPSK with some symbol permutation. Such a tripler-last 240GHz QPSK TX was reported [8]. However, a 16-QAM constellation, for example, would suffer severe distortion by frequency tripling. If the 300GHz band is to be seriously considered for a platform for ultrahigh-speed wireless communication, QAM-capability will be a requisite.

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS

An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.

CMOS 300-GHz 64-QAM transmitter

A QAM-capable 300-GHz transmitter operating above the transistor fmax, covering a 30-GHz bandwidth with multiple channels was recently reported. A key enabling component was a tripler-based up-conversion mixer called the “cubic mixer.” This paper theoretically and experimentally studies the S/N characteristics of such a mixer and elucidates the condition for realizing high single-channel data-rate. 30 Gb/s with 32QAM and 21 Gb/s with 64QAM are achieved under optimal conditions, which are faster than the previously reported per-channel data-rate of 17.5 Gb/s.

A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels

A 300 GHz transmitter (TX) fabricated using a 40 nm CMOS process is presented. It achieves 17.5 Gb/s/ch 32-quadrature amplitude modulation (QAM) transmission over six 5 GHz-wide channels covering the frequency range from 275 to 305 GHz. With the unity-power-gain frequency fmax of the NMOS transistor being below 300 GHz, the TX adopts a power amplifier-less QAM-capable architecture employing a highly linear subharmonic mixer called a cubic mixer. It is based on and as compact as a tripler and enables the massive power combining necessary above fmax without undue layout complication. The frequency-dependent characteristics of the cubic mixer are studied, and it is shown that even higher data rates of up to 30 Gb/s are possible at certain frequencies, where the channel signal-to-noise ratio is high. The design and the operation of the power-splitting and power-combining circuits are also described in detail. The measurements reported herein were all made “wired” via a WR3.4 waveguide.

300-GHz MOSFET model extracted by an accurate cold-bias de-embedding technique

This paper proposes an improved cold-bias de-embedding technique that properly separates the bias-independent parasitics from the bias-dependent core MOSFET characteristics. This is accomplished by considering possible discrepancy between dc and high-frequency I-V characteristics. It makes the core MOSFET model very simple. A 32-μm-wide common-source MOSFET fabricated in a 65 nm LP CMOS process is successfully modeled up to 330 GHz.

28mW 10Gbps transmitter for 120GHz ASK transceiver

In this paper, we describe a low-power millimeter-wave amplitude-shift-keying transmitter architecture and its design technique. This architecture adopts a push-push-type oscillator. The load-pull-like design technique for the oscillator enables us to extract large output power with the same power dissipation and to remove the power amplifier from the transmitter. The transmitter is fabricated using a 40nm CMOS technology. The core area is 0.11mm2. The measured carrier frequency is adjusted by the backgate voltages of MOSFETs centering at 122GHz. The maximum output power is +0.1dBm with 28.3mW power dissipation. The on-off ratio is 18.2dB and the maximum modulation speed is more than 10Gbps.

17.9 A 105Gb/s 300GHz CMOS transmitter

“High speed” in communications often means “high data-rate” and fiber-optic technologies have long been ahead of wireless technologies in that regard. However, an often overlooked definite advantage of wireless links over fiber-optic links is that waves travel at the speed of light c, which is about 50% faster than in optical fibers as shown in Fig. 17.9.1 (top left). This “minimum latency” is crucial for applications requiring real-time responses over a long distance, including high-frequency trading [1]. Further opportunities and new applications might be created if the absolute minimum latency and fiber-optic data-rates are put together. (Sub-)THz frequencies have an extremely broad atmospheric transmission window with manageable losses as shown in Fig. 17.9.1 (top right) and will be ideal for building light-speed links supporting fiber-optic data-rates. This paper presents a 105Gb/s 300GHz transmitter (TX) fabricated using a 40nm CMOS process.

On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz

It is known that the THRU standard (a transmission line) used for thru-reflect-line (TRL) calibration/de-embedding for S-parameter measurement has to be long enough that only a single electromagnetic mode propagates at its center for it to work reliably. But ideally, TRL standards should occupy as little precious silicon real estate as possible. This paper attempts to experimentally find out how long a THRU is long enough above 110GHz up to 170 GHz through measurements of transmission lines of various lengths. The results indicate that the length of a THRU should be at least 400 micrometers, excluding pads and pad-to-line transitions.

Characteristic impedance determination technique for CMOS on-wafer transmission line with large substrate loss

A characteristic impedance determination technique that can be used in the CMOS process with a large substrate loss is proposed. Furthermore, it is shown using image parameters that the propagation constant is obtained directly from Thru and Line without determining error networks. The validity of the characteristic impedance obtained by the proposed method is shown using the measurement and EM simulation results. The calibration patterns used for the validation check were fabricated using the 40 nm CMOS process.