Mizuki Motoyoshi

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10−9.

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS

An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.

28mW 10Gbps transmitter for 120GHz ASK transceiver

In this paper, we describe a low-power millimeter-wave amplitude-shift-keying transmitter architecture and its design technique. This architecture adopts a push-push-type oscillator. The load-pull-like design technique for the oscillator enables us to extract large output power with the same power dissipation and to remove the power amplifier from the transmitter. The transmitter is fabricated using a 40nm CMOS technology. The core area is 0.11mm2. The measured carrier frequency is adjusted by the backgate voltages of MOSFETs centering at 122GHz. The maximum output power is +0.1dBm with 28.3mW power dissipation. The on-off ratio is 18.2dB and the maximum modulation speed is more than 10Gbps.

On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz

It is known that the THRU standard (a transmission line) used for thru-reflect-line (TRL) calibration/de-embedding for S-parameter measurement has to be long enough that only a single electromagnetic mode propagates at its center for it to work reliably. But ideally, TRL standards should occupy as little precious silicon real estate as possible. This paper attempts to experimentally find out how long a THRU is long enough above 110GHz up to 170 GHz through measurements of transmission lines of various lengths. The results indicate that the length of a THRU should be at least 400 micrometers, excluding pads and pad-to-line transitions.

Characteristic impedance determination technique for CMOS on-wafer transmission line with large substrate loss

A characteristic impedance determination technique that can be used in the CMOS process with a large substrate loss is proposed. Furthermore, it is shown using image parameters that the propagation constant is obtained directly from Thru and Line without determining error networks. The validity of the characteristic impedance obtained by the proposed method is shown using the measurement and EM simulation results. The calibration patterns used for the validation check were fabricated using the 40 nm CMOS process.

Process parameter calibration for millimeter-wave CMOS back-end device design with electromagnetic field analysis

This paper presents a systematic procedure for calibrating process parameters for electromagnetic field analysis. A few CMOS back-end material parameters are first chosen as fitting parameters by sensitivity analysis, and then their values are unambiguously determined from contour maps showing electrical characteristics versus effective material parameters. Calibration with measured data for 1-170 GHz is shown to give reasonably predictive simulation even at higher frequencies. Extraction of effective complex permittivities are also attempted up to 325 GHz in the presence of dummy metal fills for two filling patterns. The results indicate that the effective-parameter approach to dummy metal fills can reproduce measured propagation constants of transmission lines. The predictive power of such a simple approach is yet to be assessed.

CMOS power amplifier with temperature compensation for 79 GHz radar system

We have developed a 79 GHz CMOS power amplifier (PA) with temperature compensation implemented using 40 nm CMOS technology that suppresses the variation of small-signal gain and the degradation of linearity within 0.8 dB in the temperature range from 0 to 100°C. The PA consists of an on-chip temperature sensor and four-stage common-source NMOS amplifiers. The temperature-compensated PA operating at 100°C achieved a small-signal gain of 15.7 dB, a 12 GHz bandwidth and a saturated output power (Psat) of 6.8 dBm with 96.2 mW power consumption at a supply voltage of 1.1 V.

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm2. It can operate with a data rate of 10Gbps.

A 0.4-ns power switching Ku-band amplifier for direct RF undersampling receiver

We have developed a high speed gate switching type Ku-band CMOS amplifier for direct RF undersampling receiver. This amplifier will synchronize its d.c. power switch timing to the sampling clock of the direct RF undersampling receiver. For Ku-band VSAT application, we designed the sampling clock frequency of undersampling receiver as 600 MHz, therefore the power switching time (Turn-On Time) of less than 0.83 ns is required. By using gate bias switching configuration, we achieve 0.4 ns power switching time by both simulation and measurement. This high speed power switching amplifier enable to reduce the d.c. power consumption about 1/2 when the 50% duty cycle of the clock for switching is applied.