Shuhei Amakawa

Single-parameter nonadiabatic quantized charge pumping

Controlled charge pumping in an AlGaAs/GaAs gated nanowire by single-parameter modulation is experimentally and theoretically studied. Transfer of integral multiples of the elementary charge per modulation cycle is clearly demonstrated. A simple theoretical model shows that such a quantized current can be generated via loading and unloading of a dynamic quasibound state. It demonstrates that nonadiabatic blockade of unwanted tunnel events can obliterate the requirement of having at least two phase-shifted periodic signals to realize quantized pumping.

1.2–17.6 GHz Ring-Oscillator-Based Phase-Locked Loop with Injection Locking in 65 nm Complementary Metal Oxide Semiconductor

A wide-frequency-range phase-locked loop (PLL) with subharmonic injection locking is proposed. The PLL is equipped with a wide tunable ring-type voltage-controlled oscillator (ring VCO), frequency dividers, and a doubler in order to the widen injection-locked tuning range (ILTR). In addition, high-frequency injection signals are used to improve phase noise, which is supposed to be generated by a reference PLL. The proposed circuit is fabricated by using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. The measured frequency tuning range is from 1.2 to 17.6 GHz with a frequency doubler and dividers. The phase noise at 14.4 GHz (=32×450 MHz) with injection locking was -109 dBc/Hz, which shows a 21-dB reduction compared with that in the case without injection locking.

20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels

The vast unallocated frequency band lying above 275GHz offers enormous potential for ultrahigh-speed wireless communication. An overall bandwidth that could be allocated for multi-channel communication can easily be several times the 60GHz unlicensed bandwidth of 9GHz. We present a 300GHz transmitter (TX) in 40nm CMOS, capable of 32-quadrature amplitude modulation (QAM) 17.5Gb/s/ch signal transmission. It can cover the frequency range from 275 to 305GHz with 6 channels as shown at the top of Fig. 20.1.1. Figure 20.1.1 also lists possible THz TX architectures, based on recently reported above-200GHz TXs. The choice of architecture depends very much on the transistor unity-power-gain frequency fmax. If the fmax is sufficiently higher than the carrier frequency, the ordinary power amplifier (PA)-last architecture (Fig. 20.1.1, top row of the table) is possible and preferable [1-3], although the presence of a PA is, of course, not a requirement [4,5]. If, on the other hand, the fmax is comparable to or lower than the carrier frequency as in our case, a PA-less architecture must be adopted. A typical such architecture is the frequency multiplier-last architecture (Fig. 20.1.1, middle row of the table). For example, a 260GHz quadrupler-last on-off keying (OOK) TX [6] and a 434GHz tripler-last amplitude-shift keying (ASK) TX [7] were reported. A drawback of this architecture is the inefficient bandwidth utilization due to signal bandwidth spreading. Another drawback is that the use of multibit digital modulation is very difficult, if not impossible. An exception to this is the combination of quadrature phase-shift keying (QPSK) and frequency tripling. When a QPSK-modulated intermediate frequency (IF) signal undergoes frequency tripling, the resulting signal constellation remains that of QPSK with some symbol permutation. Such a tripler-last 240GHz QPSK TX was reported [8]. However, a 16-QAM constellation, for example, would suffer severe distortion by frequency tripling. If the 300GHz band is to be seriously considered for a platform for ultrahigh-speed wireless communication, QAM-capability will be a requisite.

Nanoscale Coulomb blockade memory and logic devices

This paper gives a brief review of our recent work done in the area of nanometre-scale Coulomb blockade (CB) memory and logic devices, that enable us to realize future electron-number scalability by overcoming inherent problems to conventional semiconductor devices. We introduce multiple-tunnel junctions (MTJs), naturally formed in heavily doped semiconductor nanowires, as a key building block for our CB devices. For memory applications, the hybrid MTJ/MOS cell architecture is described, and its high-speed RAM operation is investigated. For logic applications the binary decision diagram logic is discussed as a suitable architecture for low-gain MTJ transistors.

A Simple Model of a Single-Electron Floating Dot Memory for Circuit Simulation

A new simulation technique for a single-electron floating dot memory based on a semiclassical single-electron transistor is proposed. It is designed to be suitable for use in circuit simulation and it uses a Monte Carlo method in combination with the master equation. Current-voltage characteristics of the sensing single-electron transistor are modeled on the steady-state master equation. Stochastic charging and discharging of the memory dot is simulated by the Monte Carlo method. Our model is faster than the master equation method alone. In addition, drain current of the transistor can be calculated accurately at every instant in the transient simulation, which is time-consuming with the conventional Monte Carlo method alone.

A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS

Design and implementation of a CMOS differential ring-VCO that locks at half-integral (1.5, 2.5, 3.5, ⋯) as well as integral (1, 2, 3, ⋯) multiples of the injected reference frequency fref are presented. The advantage of half-integral subharmonic locking is that, for a given VCO output frequency step, the output phase noise can be lowered than when using integral subharmonic locking because of the higher (2x) reference frequency. For example, the 1-MHz-offset phase noise at a VCO output frequency of 1.5GHz was −136 dBc/Hz when locked to an integral subharmonic of fref = 0.5 GHz, whereas it was as low as −139 dBc/Hz when locked to a half-integral subharmonic of fref = 1.0 GHz. The ring-VCO was fabricated with a 0.18µm CMOS process. An explanation is given as to why it locks to half-integral subharmonics and how such an oscillator could be designed. Half-integral or, more generally, nonintegral subharmonic locking could make an effective means to reduce the phase noise of high-resolution injection-locked VCOs.

Circuit Simulators Aiming at Single-Electron Integration.

We have developed two types of single-electron simulators. One is for lower level circuit simulation, denoted as extended single-electron simulator (ESS) and the other is for higher level simulation, denoted as single electron transistor-simulation program with integrated circuit emphasis (SET-SPICE). ESS simulates small-scale arbitrary circuits with precision, performs efficient steady-state analysis besides conventional transient analysis, and visualizes probability distributions. SET-SPICE, on the other hand, simulates large-scale single-electron-transistor circuits with relatively large node capacitances at high speed and performs co-simulation of single electron transistor (SET) and complementary metal oxide semiconductor (CMOS) circuits.

A scalable wideband low-noise amplifier consisting of CMOS inverter circuits for multi-standard RF receivers

This paper presents a wideband low-noise amplifier (LNA) architecture that is scalable in terms of the chip area and supply voltage and therefore is expected to offer superior performance with technology scaling. In order to secure low-voltage scalability and allow for potential rail-to-rail operation under an ultralow supply voltage, the CMOS inverter is chosen as the basic amplifier stage. The core of the LNA gain stage comprises two CMOS inverters. To realize wideband operation with area scalability, two band broadening techniques that require neither inductors nor capacitors are adopted. First, to reduce the Miller capacitance, the classic Cherry-Hooper band broadening technique is applied to the CMOS inverter-based amplifier. Second, an active frequency peaking technique is introduced with the use of feedback through another CMOS inverter. The scalability and wideband characteristics of the proposed LNA are confirmed by comparing chips fabricated using 180nm and 90nm CMOS process technologies. The LNA in 90nm CMOS achieved 18.0 dB gain, 0.1–6.8GHz bandwidth, 3.0–5.5 dB noise figure, and 14.5mW power dissipation with occupying only 0.0032mm2, which is 48% of the 180nm CMOS LNA area.

A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

A 9.5 mW 20 Gb/s 40×70 ¿m2 inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralow-voltage many-core era.

CMOS 300-GHz 64-QAM transmitter

A QAM-capable 300-GHz transmitter operating above the transistor fmax, covering a 30-GHz bandwidth with multiple channels was recently reported. A key enabling component was a tripler-based up-conversion mixer called the “cubic mixer.” This paper theoretically and experimentally studies the S/N characteristics of such a mixer and elucidates the condition for realizing high single-channel data-rate. 30 Gb/s with 32QAM and 21 Gb/s with 64QAM are achieved under optimal conditions, which are faster than the previously reported per-channel data-rate of 17.5 Gb/s.