Kyoya Takano

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Recently, short-distance high-speed wireless communication using a 60 GHz band has been studied for mobile application. To realize higher-speed wireless communication while maintaining low power consumption for mobile application D band (110-170 GHz) is promising since it can potentially provide a wider frequency band. Thus, we have studied D-band CMOS circuits to realize low-power ultrahigh-speed wireless communication. In the D band, however, since no sufficient device model is provided, research generally has to start from device modeling. In this paper, a design procedure for D-band CMOS circuits is overviewed from the device layer to the system layer, where the architecture is optimized to realize both low power and high data transfer rate. Finally, a 10 Gbps wireless transceiver with a power consumption of 98 mW is demonstrated using the 135 GHz band.

4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking

To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFYM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 mum 1P5M CMOS process. The core size was 10.8 mum x 10 S mum. The power consumption of the ILO is 9.6 muW at 250 MHz, and 1.47 mW at 4.8 GHz. The phase noise is -108 dBc/Hz at 1 MHz offset. For a ten-times frequency multiplier, output phase noise is 10 JB larger than the input phase noise below 10 kHz offset, which is the theoretical limit.

A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology

The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10−9.

20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels

The vast unallocated frequency band lying above 275GHz offers enormous potential for ultrahigh-speed wireless communication. An overall bandwidth that could be allocated for multi-channel communication can easily be several times the 60GHz unlicensed bandwidth of 9GHz. We present a 300GHz transmitter (TX) in 40nm CMOS, capable of 32-quadrature amplitude modulation (QAM) 17.5Gb/s/ch signal transmission. It can cover the frequency range from 275 to 305GHz with 6 channels as shown at the top of Fig. 20.1.1. Figure 20.1.1 also lists possible THz TX architectures, based on recently reported above-200GHz TXs. The choice of architecture depends very much on the transistor unity-power-gain frequency fmax. If the fmax is sufficiently higher than the carrier frequency, the ordinary power amplifier (PA)-last architecture (Fig. 20.1.1, top row of the table) is possible and preferable [1-3], although the presence of a PA is, of course, not a requirement [4,5]. If, on the other hand, the fmax is comparable to or lower than the carrier frequency as in our case, a PA-less architecture must be adopted. A typical such architecture is the frequency multiplier-last architecture (Fig. 20.1.1, middle row of the table). For example, a 260GHz quadrupler-last on-off keying (OOK) TX [6] and a 434GHz tripler-last amplitude-shift keying (ASK) TX [7] were reported. A drawback of this architecture is the inefficient bandwidth utilization due to signal bandwidth spreading. Another drawback is that the use of multibit digital modulation is very difficult, if not impossible. An exception to this is the combination of quadrature phase-shift keying (QPSK) and frequency tripling. When a QPSK-modulated intermediate frequency (IF) signal undergoes frequency tripling, the resulting signal constellation remains that of QPSK with some symbol permutation. Such a tripler-last 240GHz QPSK TX was reported [8]. However, a 16-QAM constellation, for example, would suffer severe distortion by frequency tripling. If the 300GHz band is to be seriously considered for a platform for ultrahigh-speed wireless communication, QAM-capability will be a requisite.

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS

An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.

8Gbps CMOS ASK modulator for 60GHz wireless communication

In this paper we present a millimeter-wave CMOS amplitude-shift-keying (ASK) modulator for 60 GHz wireless communication at greater than 1 Gbps. It is designed using shunt NMOSFET switches between the signal and the ground line of a transmission line. A reduced-switch architecture is used to achieve high speed. The transmission line length between switches is adjusted to achieve high isolation with a reduced number of switches. A 60 GHz millimeter-wave ASK modulator is successfully realized by using a 6-metal 1-poly 90 nm CMOS process. The size of the chip is 0.8 mm times 0.48 mm including the pads. The core size is 0.61 mm times 0.3 mm. The isolation and maximum data rate of the modulator at 60 GHz are measured to be 26.6 dB and 8 Gbps, respectively. The product of the maximum data rate and the isolation of this modulator is 170 GHz, which is the highest value among over-Gbps ASK modulators.

CMOS 300-GHz 64-QAM transmitter

A QAM-capable 300-GHz transmitter operating above the transistor fmax, covering a 30-GHz bandwidth with multiple channels was recently reported. A key enabling component was a tripler-based up-conversion mixer called the “cubic mixer.” This paper theoretically and experimentally studies the S/N characteristics of such a mixer and elucidates the condition for realizing high single-channel data-rate. 30 Gb/s with 32QAM and 21 Gb/s with 64QAM are achieved under optimal conditions, which are faster than the previously reported per-channel data-rate of 17.5 Gb/s.

A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels

A 300 GHz transmitter (TX) fabricated using a 40 nm CMOS process is presented. It achieves 17.5 Gb/s/ch 32-quadrature amplitude modulation (QAM) transmission over six 5 GHz-wide channels covering the frequency range from 275 to 305 GHz. With the unity-power-gain frequency fmax of the NMOS transistor being below 300 GHz, the TX adopts a power amplifier-less QAM-capable architecture employing a highly linear subharmonic mixer called a cubic mixer. It is based on and as compact as a tripler and enables the massive power combining necessary above fmax without undue layout complication. The frequency-dependent characteristics of the cubic mixer are studied, and it is shown that even higher data rates of up to 30 Gb/s are possible at certain frequencies, where the channel signal-to-noise ratio is high. The design and the operation of the power-splitting and power-combining circuits are also described in detail. The measurements reported herein were all made “wired” via a WR3.4 waveguide.

Phase-sensitive Amplifier Based on Two-pump Four-wave Mixing in an Optical Fiber

We demonstrate a novel scheme of fiber-based phase-sensitive amplifiers using two-pump degenerate four-wave mixing. Phase-sensitive gain ranging from 5dB to -4.5dB is obtained in a simple straight-line configuration composed of a 1-km-long highly nonlinear fiber.

300-GHz MOSFET model extracted by an accurate cold-bias de-embedding technique

This paper proposes an improved cold-bias de-embedding technique that properly separates the bias-independent parasitics from the bias-dependent core MOSFET characteristics. This is accomplished by considering possible discrepancy between dc and high-frequency I-V characteristics. It makes the core MOSFET model very simple. A 32-μm-wide common-source MOSFET fabricated in a 65 nm LP CMOS process is successfully modeled up to 330 GHz.