Kozaburo Kurita

CMOS/bipolar circuits for 60-MHz digital processing

High-performance bipolar/CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 4-GHz cutoff frequency is combined with standard CMOS devices on the same chip, has been applied to a processor. The design strategy was to provide high integration density using the CMOS circuit and accelerate the critical paths using the Hi-BiCMOS circuits. Hi-BiCMOS circuits with low-voltage swing have been developed and applied to a 32-bit arithmetic logic unit and a 128-kb ROM with bipolar drivers to drive a heavy load capacitance. A 17-ns 32-bit carry propagation delay time and a 17-ns ROM access cycle time have been achieved using 2-/spl mu/m Hi-BiCMOS technology. A minicomputer CPU with a 60-MHz machine cycle can be implemented with these circuits.

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 mu m for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circuits for a 32-bit ALU, 4-kbyte/17-ns cache memory including an address translation function, and a 64-bit/37-ns multiplier. High integration density is obtained by using CMOS-based circuits and fast operation is achieved by using CMOS/bipolar sense circuits and drivers. In the cache memory, a functional sense amplifier, in which a conventional sense amplifier and a comparator are merged, is used. How to combine CMOS and bipolar devices in the macrocells along with application of the library to the VLSI computers is discussed. >

PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed using 1.0-mm BiCMOS technology. In order to obtain a very wide operation bandwidth, it is proposed that the PCG included a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the vibration bandwidth of the VCO according to the reference clock frequency, preventing the expected vibration frequency from being outside the vibration bandwidth. Therefore, the operation bandwidth of the PCG is from 3 MHz to 90 MHz. If semiconductor technology is enhanced, it should be possible to realize a clock generator operating near 200 MHz