Tetsuo Nakano

A 120-MHz BiCMOS superscalar RISC processor

A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm/spl times/16.5 mm, and utilizes 3.3 V/0.5 /spl mu/m BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design. >

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor. >

PLL-based BiCMOS on-chip clock generator for very high speed microprocessor

A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed using 1.0-mm BiCMOS technology. In order to obtain a very wide operation bandwidth, it is proposed that the PCG included a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the vibration bandwidth of the VCO according to the reference clock frequency, preventing the expected vibration frequency from being outside the vibration bandwidth. Therefore, the operation bandwidth of the PCG is from 3 MHz to 90 MHz. If semiconductor technology is enhanced, it should be possible to realize a clock generator operating near 200 MHz

Doping Effect of Oxygen on Horizontal Bridgman Grown InP

The doping effect of oxygen in melt grown InP was investigated by both Hall measurement and thermodynamical analysis. In the case when an oxygen doped crystal was grown only in the high-temperature zone, the carrier concentrations were reduced considerably due to the decrease of Si concentration in the InP crystal, and this was explained satisfactorily by the thermodynamical calculations on InP-In2O3 system. Hall measurement up to a high temperature revealed that the oxygen atoms did not behave as shallow nor deep impurities in the crystal.

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

3.3-V, high-speed circuit techniques, including a 0.6-ns single-ended common-base sense circuit, a 0.5-ns 22-b comparator circuit, and a 0.7-ns 3-input adder circuit, are applied to a 2.8-million-transistor RISC (reduced instruction set computer) microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS 3.3-V 4-metal-layer technology. The chip includes a 240-MFLOPS (million floating point operations per second) double-precision floating-point unit and a 24-kByte cache, and dissipates 17 W at 120 MHz.

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

A BiCMOS 32-bit execution has been developed to attain 70-MHz (typical) speed using 1.0-μm BiCMOS technology. The three important components are: (1) an arithmetic unit, which uses a 0.6-ns 8-bit carry propagation circuit; (2) a 2.5-ns 54-W×32-b four-port register file, which uses a BiCMOS sense circuit and dynamic bus drivers; and (3) a flag generator, which uses a novel all-bit-zero generation algorithm and generates in parallel with the arithmetic computation. A CLSI computer has been implemented with the above components, and 70-MHz register-register operation has been achieved