Kris G. Konigsfeld

Microarchitecture evaluation with floorplanning and interconnect pipelining

As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple cycles will be necessary to communicate global signals across the chip. Thus, longer interconnects need to be pipelined, and the impact of the extra latency along wires needs to be considered during early microarchitecture design exploration. In this paper, we address this problem and make the following contributions: (1) a floor plan-driven microarchitecture evaluation methodology considering interconnect pipelining at a given target frequency by selectively optimizing architecture level critical paths; (2) use of microarchitecture performance sensitivity models to weight microarchitectural critical paths during floor planning and optimize them for higher performance; and (3) a methodology to study the impact of frequency scaling on microarchitecture performance with consideration of interconnect pipelining. For a sample microarchitecture design space, we show that considering interconnect pipelining can increase the estimated performance against a no wire pipelining approach between 25% to 45%. We also demonstrate the value of the methodology in exploring the target frequency of the processor.

The next HDL (panel session): if C++ is ;the answer, what was the question?

The focus of this panel is on issues surrounding the use of C++ in modeling, integration of silicon IP and system-on-chip designs. In the last two years there have been several announcements promoting C++ based solutions and of multiple consortia (SystemC, Cynapps, Accellera, SpecC) that represent increasing commercial interest both from tool vendors as well as perhaps expression of genuine needs from the design houses. There are, however, serious questions about what value proposition does a C++ based design methodology bring to the IC or system designer? What has changed in the modeling technology (and/or available tools) that gives a new capability? Is synthesis the right target? or VAlidation? Tester modeling or testbench generation? This panel brings together advocates and opponents from the user community to highlight the achievements and the challenges that remain in use C++ for use in microelectronic circuits and systems.