Paul D. Madland

High performance circuits for the i486 processor

Three high-performance circuit blocks of the i486 processor are described: a large, on-chip cache; a 1* clock generator; and a high-speed, 32-b adder. In addition, a summary of the methodology used to design these circuits are given. The circuit used to regulate the clock duty cycle used a feedback technique to adjust timer delays, preventing clock overlap. The timer circuit uses current mirror transistors and capacitors to create a delay interval controlled by the reference voltages. The 1* clock circuit on the i486 processor eases board design requirements by eliminating the need for double frequency clocks with tight timing.<<ETX>>