Ralph Bishop

A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

A fully integrated four-channel multi-antenna receiver intended for beamforming and spatial diversity applications is presented. It can also be used as a low-power area-efficient range extender for spatially multiplexed multi-antenna systems that are poised to become mainstream in the near future. Implemented in a 90-nm CMOS technology, each channel weights its input signal by a complex weight with full 360/spl deg/ phase shift programmability using vector combinations of variable-gain amplifiers, thus obviating the need for expensive phase shifters. The chip consumes 140 mW from a single 1.4-V supply and achieves 12 dB of array gain with all four channels activated and >20 dB direction-of-arrival-dependent interference rejection.

64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method

A method to optimally pump energy from the transistors to the passive network is presented for the design of integrated 64 GHz and 100 GHz VCOs in 90 nm CMOS. The VCOs use an on-die distributed network, draw /spl sim/25 mA from a 1 V supply and produce oscillations with 0.4 Vp-p amplitudes. Phase noise is <-110 dBc/Hz at 10 MHz offset, and VCO gain is 2 GHz/V.

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

A 5-bit flash ADC incorporates 20 mum by 20 mum inductors to improve both comparator preamplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for a 1 GHz input at 3.5 GS/s. The power consumption (including clock buffer and ladder) is 227 mW at 3.5 GS/s. The active area is 0.658 mm2

An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process

We present a 5 GHz, voltage controlled quadrature oscillator, based on transformer coupling between the quadrature components. The oscillator is fabricated in a 0.18 /spl mu/m, low voltage digital CMOS process with a lossy substrate (/spl rho//spl sim/10mohm-cm) and thin, high resistivity metallization. Fully integrated low Q (/spl sim/4) spirals form the transformer windings in the resonators. The coupling has been optimized to obtain quadrature accuracy with minimum phase noise degradation. The VCO achieves a tuning range of /spl sim/1 GHz, and a phase noise of up to -123 dBc/Hz at a 1 MHz offset, while drawing 7.5 mA at 1.6 V. An image reject receiver built using the onwafer quadrature signals, provides 43 dB of image rejection, confirming better than 1/sup 0/ of quadrature matching.

A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications

A 90nm CMOS four-channel analog beamforming receiver draws 140mW at 1.4V and achieves 6dB SNR improvement with 360/spl deg/ look-angle coverage and 20dB interference cancellation. Vector combinations of programmable gain elements eliminate the need for explicit phase shifters. The analog combining technique is also useful as a low-power range extender/interference canceller in conjunction with spatial-multiplexing MIMO.

A highly linear filter and VGA chain with novel DC-offset correction in 90nm digital CMOS process

This paper presents a complete base-band chain for current and emerging WLAN in 1.4V 90nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 1/10/100MHz filter and five VGA stages. The design is DC-offset free and uses optimized Gm stages for linearity and low voltage operation. IIP3 is 2dBm @ 13.5dB minimum gain, while dissipating 13.5mW.

A 1.4V, 13.5mW, 10/100MHz 6/sup th/ order elliptic filter/VGA with DC-offset correction in 90nm CMOS [WLAN applications]

This paper presents a complete base-band chain for WLAN applications in 1.4 V 90 nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 10/100 MHz filter and five VGA stages. The design is DC-offset free and uses optimized transconductance for linearity and low-voltage operation. Moreover, the integrators in the filter are compensated for losses through a frequency transformation. The IIP3 is 2 dBm at 13.5 dB minimum gain, while dissipating 13.5 mW.

A 90nm CMOS Doherty Power Amplifier with Integrated Hybrid Coupler and Impedance Transformer

An OFDM capable Doherty PA is implemented in 90 nm CMOS with integrated quadrature hybrid and impedance transformer. The two amplifiers are optimized to minimize AM-PM distortion. The PA achieves 25 dBm Psa, using 1.4 V supply with 24% PAE, and operates over 1 GHz of frequency range (from 4 GHz to 5 GHz). 3 dB to 6 dB back-off from P1dB is required to achieve -25 dB measured EVM across this band, making it suitable for WLAN and WiMAX applications. The measured AM-PM distortion varies from 4deg to 12.5deg across the 1 GHz range.

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS

A 5GHz 2times2 MIMO transceiver in 90nm CMOS supports spatial multiplexing and diversity, achieving 54/108Mb/s with -75/-63dBm sensitivity for an AWGN/25ns-Rayleigh channel, respectively. Each RX draws 120mA from a 1.4V supply. Each 3.3V 5GHz PA delivers +16/+13dBm average power with -25/-27dB EVM in 1times1/2times2 modes, respectively. The system-in-package including microstrip front-end matching on a flip-chip package occupies a die area of 18mm2