Shyh-Shyuan Sheu

Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

A 30×30 nm2 HfOx resistance random access memory (RRAM) with excellent electrical performances is demonstrated for the scaling feasibility in this work. A 1 Kb one transistor and one resistor (1T1R) array with robust characteristics was also fabricated successfully. The device yield of the 1 Kb array is 100%, and the endurance for these devices can exceed 106 cycles by a pulse width of 40 ns. Two effective verification methods, which make a tight distribution of high resistance (RHIGH) and low resistance (RLOW) are proposed for the array to ensure a good operation window. A thin AlOx buffer layer under the HfOx layer was adopted to enhance the read disturb immunity. Without large parasitic capacitance, the 1T1R RRAM devices exhibit excellent program(PGM)/erase(ERS) disturb immunity.

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

Evidence and solution of over-RESET problem for HfO X based resistive memory with sub-ns switching speed and high endurance

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications

This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

Fast-Write Resistive RAM (RRAM) for Embedded Applications

Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC

Mobile systems require high-performance and low-power SoC or 3D-IC chips to perform complex operations, ensure a small form-factor and ensure a long battery life time. A low supply voltage (VDD) is frequently utilized to suppress dynamic power consumption, standby current, and thermal effects in SoC and 3D-IC. Furthermore, lowering the VDD reduces the voltage stress of the devices and slows the aging of chips. However, a low VDD for embedded memories can cause functional failure and low yield. This paper reviews various challenges in the design of low-voltage circuits for embedded memory (SRAM and ROM). It also discusses emerging embedded memory solutions. Alternative memory interfaces and architectures for mobile SoC and 3D-IC are also explored.

Three-dimensional 4F 2 ReRAM cell with CMOS logic compatible process

A new three dimensional vertical bipolar junction transistor (BJT) ReRAM cell with CMOS compatible process is reported. A new logic compatible BJT is vertically formed underneath the resistive stacked film of TiN/Ti/HfO2/TiN as a high performance current driver and bit-cell selector. Using a shallow and tiny NLDD to be an emitter connects with ReRAM film as the bitline, a very thin and self-aligned P-pocket implant to be the wordline, and the N-well is the collector of cells. As a result, the new 3D vertical ReRAM cell is very area-saving and efficiently operated by the high gain (β>50) BJT with a low voltage of 2V for reset and 1.5V for set. By adapting the highly shrinkable 3D BJT current driver in ReRAM, the cell is decoupled with gate length and oxide thickness of logic MOSFETs so that it can be easily scaled down to 4F2 by the lithographic limitation of defining ReRAM film with F2 area.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

Challenges and opportunities for HfO X based resistive random access memory

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm×35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes. The 28nm Contact RRAM cell exhibits a stable operation window with a very small cell size of 0.03μm2. Due to the scale down and uniform manufacturing process, the cell reliably operates in a low set voltage of 3V and an acceptable reset current of 60μA/cell with short set and reset time of 500ns and 100us. Excellent endurance of more than 1M cycles and stable data retention at high temperature further support the 28nm Contact RRAM will be a promising SOC memory i n the future.