Dong-il Bae

Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even with a long channel length, while pMOS is free of such degradation. This observation is reproduced and analyzed by a well-calibrated TCAD simulation deck with Qf introduced. A new Fin profile suppressing the Qf effect is proposed, and the benefits of the new profile are predicted in terms of variability reduction and mobility improvement, as well as Qf immunity.

Acceptor-like trap effect on negative-bias temperature instability (NBTI) of SiGe pMOSFETs on SRB

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (Ev) lowers the Eox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

Improvement of metal photo process margin with OPC and CMP for 0.14 μm DRAM technology node and beyond

In this paper, we report highly effective Optical Proximity Correction (OPC) techniques to improve the process margin in the photo lithography process of metal layer, which can be applied to 0.14 micrometer DRAM technology node and beyond. The proposed test pattern reflects the optical limitation of each situation, the rules can be established by simply investigating the test patterns which solves the problems such as lack of contact overlap margin, line-end shortening, and size reduction in isolated and island patterns. This sophisticated rule is considering the vertical environment as well. Thanks to systematic sequence for rule extraction, we could minimize additional burdens such as error occurrence, rule set-up time, data volume, manufacturing time of mask. By applying this method, DOF margin of metal layer could be improved from 0.4 micrometer to beyond 0.6 micrometer, which provides sufficient process window for mass production of 0.14 micrometer DRAM technology. In addition, we also confirmed that the new OPC technology could be extended to the metal layer of 0.11 micrometer DRAM.