Kunal Vaed

A new on-wafer de-embedding technique for on-chip rf transmission line interconnect characterization

Absfracf This paper introduces a new de-embedding method for on-chip RF transmission line characterization. The new technique allows subtraction of pad parasitics based on measurements of only two LI=L and Lz=N.L (N being a discrete number) long transmission lines with attached measurement pads. No dummy “open”, “short” and “thru” devices are required. The new method has also been extended for the case when Lz#N.L, and only L,, L2 and AL= L,-L, long interconnects with attached pads are available on the test wafer. The proposed methodology has been compared with several well-known de-embedding approaches (“thru”, “open-short” aed “short-open“) and with simulation results from the industry standard electromagnetic solver (lE3D) for de-embedding of on-chip interconnects at frequencies up to 70GHz. Index Terms -Transmission Line interconnect, on-wafer measurement, S-parameters, de-embedding.

A manufacturable high-k MIM dielectric with outstanding reliability and voltage linearity for RF and mixed-signal technologies

We demonstrate the simultaneous optimization of 100,000 POH reliability and voltage linearity (<40 ppm/V) for a high-k MIM dielectric (4.5 fF/m/sup 2/) that is both Al and Cu BEOL compatible. Also, we discuss the scaling of dielectric films to achieve excellent bias linearity, while attaining a capacitance density of 7.2 fF/m/sup 2/.

Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides

This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chips metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.

High-performance thick copper inductors in an RF technology

With the emergence of wired and wireless communication technologies, on-chip inductors find applications in a variety of high performance radio frequency (RF) circuits. In this work, we present two approaches for high-performance copper inductors in an RF technology. In the first approach (Type I), we lower ohmic losses to realize a high Q-factor. This is achieved by using, for the first time in a manufacturable technology, 4 μm thick copper spirals along with a 4 μm thick copper underpass on high-resistivity substrates (75 Ω-cm). The underpass is connected to the spirals with a 4 μm tall copper via, which lowers spiral to underpass capacitance. For further lowering the capacitive losses, an additional 6.1 μm thick interlayer dielectric separates the underpass from the substrate. In the second approach (Type II), we utilize a novel one-mask CMOS-compatible micromachining scheme to eliminate substrate losses. This is achieved by completely removing the silicon substrate from directly below the inductors. For a 1.1nH inductor, peak-Q shows an impressive two-fold improvement from 26.6 at 3.8 GHz for Type I inductor to 52.8 at 8.2 GHz for Type II inductor after silicon micromachining. The resonant frequency increases from 18 GHz to 27 GHz after substrate micromachining.