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Dive into the research topics where Kunihiro Fujiyoshi is active.

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Featured researches published by Kunihiro Fujiyoshi.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1996

VLSI module placement based on rectangle-packing by the sequence-pair

Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani

The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.


international conference on computer aided design | 1995

Rectangle-packing-based module placement

Hiroshi Murata; Kunihiro Fujiyoshi; Shigetoshi Nakatake; Yoji Kajitani

The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular modules of arbitrary site, place them without overlapping on a layer in the smallest bounding rectangle. Since the variety of the packing is infinite (two-dimensionally continuous) many, the key issue for successful optimization is in the introduction of a P-admissible solution space, which is a finite set of solutions at least one of which is optimal. This paper proposes such a solution space where each packing is represented by a pair of module name sequences. Searching this space by simulated annealing, hundreds of modules could be successfully packed as demonstrated. Combining a conventional wiring method, the biggest MCNC benchmark ami49 is challenged.


asia and south pacific design automation conference | 1997

A mapping from sequence-pair to rectangular dissection

Hiroshi Murata; Kunihiro Fujiyoshi; Tomomi Watanabe; Yoji Kajitani

A fundamental issue in floorplanning is in how to represent candidate solutions. A representation called sequence-pair was recently proposed. Seq-pair is so general as to represent an area minimum placement, and also efficient because it does not represent any overlapping placement. However, seq-pair is not expressive enough since channels are not represented. The paper gives a mapping from seq-pair to rectangular dissection, which represents channels by line segments. Consequently, candidate arrangements of modules and channels are successfully represented with the generality and the efficiency inherited from the seq-pair.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2000

Arbitrary convex and concave rectilinear block packing using sequence-pair

Kunihiro Fujiyoshi; Hiroshi Murata

The sequence-pair was proposed in 1995 as a representation of the packing of rectangles of general structure. Since then, there have been efforts to expand its applicability over simple rectangles. This paper proposes a unified way to represent the packing of a set of rectilinear blocks, including arbitrary concave rectilinear blocks. Our idea is in the representation of a general block by a collection of rectangle blocks with additional constraints, Some sequence-pairs of rectangle blocks with such constraints may not be feasible, i.e., there is no corresponding parking. A necessary and sufficient condition of feasible sequence-pair is given by the properties of the horizontal and vertical constraint graphs. Furthermore, it is proved that any packing is represented by a feasible sequence-pair. The condition includes dimensions of blocks involved. If we limit the rectilinear blocks to L-shaped ones, a necessary and sufficient condition can be represented only in terms of the topology of the sequence-pair, without dimensions of blocks. A packing algorithm is designed as an SA search of the generated sequence-pairs. Experimental results show the effectiveness of the proposed method.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2007

Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout

Shinichi Koda; Chikaaki Kodama; Kunihiro Fujiyoshi

In recent high-performance analog integrated circuit design, it is often required to place some cells symmetrically to a horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement that satisfies the given symmetry constraints and the topology constraints imposed by a sequence-pair (seq-pair). However, this method has the following defects: 1) Balasas necessary condition for existence of the cell placement that satisfies the given constraints is incorrect; 2) some cells overlap; 3) the closest placement of satisfying both the symmetry and topology constraints is not always obtained; and 4) there is no explanation of placing cells symmetrically to plural axes. In this paper, we clarify the necessary and sufficient conditions for the existence of the cell placement that satisfies the given symmetry constraints and the topology constraints imposed by a seq-pair, and we propose an efficient method of obtaining, by linear programming, the closest cell placement that satisfies the given constraints. Here, a simple constraint graph is obtained from a seq-pair in order to derive a set of linear constraint expressions. Then, to shorten the running time of linear programming, the number of linear expressions is reduced by substituting the expressions for dependent variables, and the solution is obtained. The effectiveness of the proposed method was shown by computational experiments


international symposium on physical design | 2006

Improved method of cell placement with symmetry constraints for analog IC layout design

Shinichi Kouda; Chikaaki Kodama; Kunihiro Fujiyoshi

Recently, it is often required in high performance analog IC design that some cells are placed symmetrically to horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair, but this method has the following defects: (1) Some cells overlap each other. (2) The closest cell placement satisfying both the symmetry and topology constraints may not be obtained. (3) How to place cells symmetrically is mentioned only for one axis and there is no explanation for plural axes. In this paper, we propose an efficient method to obtain the closest cell placement satisfying the given symmetry constraints and the topology constraints imposed by a sequence-pair using linear programming. The proposed method obtains a simple constraint graph from a sequence-pair and derives a set of linear constraint expressions from the graph. The number of linear expressions decreases by substituting the expressions for dependent variables. Then the solutions are obtained by linear programming. The effectiveness of the proposed method was shown by computational experiments.


international symposium on circuits and systems | 2000

Simulated annealing search through general structure floorplans using sequence-pair

K. Kiyota; Kunihiro Fujiyoshi

VLSI floorplan is a rectangular dissection of a chip rectangle where dissection lines correspond to wiring channels and each module is assigned to a separate room. Floorplans are often represented by the slicing structures. Recently, sequence-pair (seq-pair) has been proposed as the description of the rectangle packing and later on a method to map a seq-pair to a floorplan has been proposed. However, such floorplans made of seq-pairs often include rooms with no module assigned, and so it is difficult to make good solution space by seq-pair. In this paper, we propose a novel solution space of floorplans for simulated annealing (SA) which consists of the all general floorplans with exact n rooms, where n is the number of given modules, using seq-pair. By using ingenious data structure, a feasible adjacent floorplan can be obtained in O(n/sup 2/) time and the reachability from any floorplan to any other in the proposed solution space is proved. The experimental results show the effectiveness of the solution space.


international symposium on circuits and systems | 2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems

Yukihide Kohira; Chikaaki Kodama; Kunihiro Fujiyoshi; Atsushi Takahashi

In our dynamically reconfigurable system model, computation resources are arranged in 2D-plane and each partial task is assigned to computation resources of rectangle-shape for a certain time period. The problem can be regarded as a rectangular box packing problem in 3D-space of 2D-plane and time axis. However, since partial tasks have order constraints, a packing should satisfy the given order constraints. We call this problem 3D-scheduling problem. Although there have been proposed various types of rectangular box packing representation, it is not examined until now which representation is fit to 3D-scheduling problem. In this paper, we investigate features of each 3D-packing representation, and show which representation is fit to 3D-scheduling problem theoretically and experimentally


international symposium on circuits and systems | 2007

DTS: A Tree Based Representation for 3D-Block Packing

Kunihiro Fujiyoshi; Hidenori Kawai; Keisuke Ishihara

3D packing problem is to arrange rectangular boxes (blocks) of given sizes in a rectangular box of the minimum volume without overlapping each other. As a representation for 3D packings, this paper proposes a novel encoding method, called DTS (double tree and sequence). The feature of the DTS is: (1) It can represent any minimal packings. (2) The size of the solution space (the number of codes) of DTS is much smaller than any conventional representation which can represent any packings. Experimental comparisons with conventional representations indicate the superiority of the proposed representation DTS


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2009

A Tree Based Novel Representation for 3D-Block Packing

Kunihiro Fujiyoshi; Hidenori Kawai; Keisuke Ishihara

The 3D packing problem consists of arranging nonoverlapping rectangular boxes (blocks) of given sizes in a rectangular box of minimum volume. As a representation of 3D packings, this paper proposes a novel encoding method called Double Tree and Sequence (DTS). The following are features of DTS: 1) It can represent any minimal packing. 2) It can be decoded into the corresponding 3D packing in O(n 2) time, where n is the number of rectangular boxes. 3) The size of the solution space (the number of codes) of DTS is significantly smaller than any conventional representation that can represent any packing. Experimental comparisons with conventional representations indicate the superiority of the proposed representation DTS.

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Yoji Kajitani

Tokyo Institute of Technology

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Hiroshi Murata

Japan Advanced Institute of Science and Technology

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Hidenori Ohta

Tokyo University of Agriculture and Technology

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Hiroshi Niitsu

Japan Advanced Institute of Science and Technology

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