Kuo-Hsuan Lo

0.18um BCD technology with best-in-class LDMOS from 6 V to 45 V

We propose a novel nLDMOS structure and a design concept in BCD technology with the best-in-class performance. The drift profile is optimized and the multi-oxide in the drift region is adopted to approach the RESURF limit of on-resistance vs. BVdss characteristic (i.e., 36V DMOS has a Ron_sp of 20mohm-mm2 with a BVdss of 50V; 45V DMOS has a Ron_sp of 28mohm-mm2 with a BVdss of 65V). Moreover, this modification requires merely three extra masks in the Non-Epitaxy LV process to achieve this improvement. Therefore it is not only a high performance but also a low cost solution.

Ultralow Capacitance Transient Voltage Suppressor Design

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for highspeed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability.

Improving the Electrostatic Discharge Robustness of a Junction Barrier Schottky Diode Using an Embedded p-n-p BJT

The high-voltage (H-V) junction barrier Schottky (JBS) diode is often incorporated into the input or output of H-V integrated circuits. When the chip is connected to the external environment, it inevitably suffers electrostatic discharge (ESD) stress. However, the JBS diode can only withstand the forward-mode ESD but it is highly vulnerable to reverse-mode ESD. In this letter, a new kind of JBS diode that is incorporated with a p-n-p bipolar is developed. The experimental results demonstrated that the new device can improve the failure threshold voltages of the human body mode and machine mode by at least four times. The area increase for the new device is 2.2%.

Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure

In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively.

A novel 80 V HS-DMOS with gradual-RESURF profile to reduce Ron_sp for high-side operation

The Ron sp of a DMOS operated at high side (Ron_sp_HS) in the power management ICs is usually underestimated by taking the measured value at low side operation (Ron_sp_LS). The Ron_sp_HS is increased drastically when a revise voltage is applied between drift region and substrate because the drift-region is depleted and the current path is narrowed. In this paper, a novel structure with a varying-junction-depth profile in the drift region is proposed to suppress the increase of Ron_sp_HS by adding a partial n-type buried layer (NBL) under the drain region. The drift region of HS-DMOS will generate a gradual pinch-off region from channel to drain when it is operated at 80V under high side operations, and the increased percentage in Ron_sp_HS is suppressed from 128% to 79% because it allows a wider electron current flow through the neutral region of the drift region in the proposed structure.

Demonstration of a HV BCD technology with LV CMOS process

Conventional BCD and high voltage technologies are developed with extra masks and additional thermal drive-in process units included in existing LV platforms. The technology development is time-consuming and the turnaround time for the whole process takes longer. In this paper, a low cost solution with a set of layout design methodology is proposed to accomplish the embedded power BCD technology in the existing 5V CMOS process without any additional process steps.