Kuo-Pin Chang

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the worlds first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BLs (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it's Program Inhibit Characteristics

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BLs in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BLs are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.

Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash

We report for the first time a fast initial charge loss (within 1 sec) in charge-trapping (CT) NAND devices. Using a fast-response pulse I–V system retention transients from μsec to sec are characterized and the correlation with programmed states Vt distribution in various NAND Flash test chips is examined. We clarify that the impacts of fast initial charge loss are: (1) it produces a programmed state Vt offset in the various program-verify (PV) levels, and (2) it broadens the Vt distribution thus threatens the MLC capability. Our findings suggest that both high-K/metal-gate and barrier engineered tunneling barrier approaches should be optimized in order to minimize the initial charge loss. We also propose a “refill” method to suppress this effect, and have successfully demonstrated tight Vt distributions in a BE-SONOS CT NAND test chip.

Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs

A complementary metal oxide semiconductor (CMOS)-compatible WOx based resistive memory has been developed. The WOx memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (?2 ns) and the programming voltage (<1.4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 108-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WOx resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.

Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform CBLs for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

Multi-Level Switching Characteristics for WOX Resistive RAM (RRAM)

Emerging Central Lab, Macronix International Co., Ltd. Science Park, Hsinchu 300, Taiwan, R.O.C. Phone: +886-3-5786688 E-mail: wcchien@mxic.com.tw Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, 300, Taiwan, R.O.C. Department of Materials Engineering, Tatung University, Taipei, 104, Taiwan, R.O.C.

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.

A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability

This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >100K P/E cycling endurance for SLC and >3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN [1,2]. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.

A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity

We demonstrate a novel vertical channel 3D NAND Flash architecture - SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ~10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.