Hang-Ting Lue

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

Study of sub-30nm thin film transistor (TFT) charge-trapping (CT) devices for 3D NAND flash application

Sub-30nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory window is also larger than the bulk planar devices due to the tri-gate structure that enhances the electric field during programming/erasing. However, a fair percentage of devices contain grain boundaries with poorer S.S. and gm. Interestingly, this only affects the DC characteristics but does not impact the memory window. Furthermore, grain boundaries do not increase the random telegraph noise. The most serious drawback of grain boundaries is the impact on self-boosting window caused by junction leakage. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the worlds first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance

A novel 2-bit/cell nitride storage flash memory is proposed. It uses conventional CHE (channel hot electron) programming, BTBT HH (band-to-band tunneling hot hole) erase, and a unique negative FN (Fowler-Nordheim) reset, executed on p/sup +/-gate devices. Periodic -FN resets can restore V/sub t/ operation window by removing hard-to-erase electrons trapped in the channel center and neutralizing holes trapped in ONO regions above the junctions. We report, for the first time, the achieving of 10M P/E-cycle endurance in nitride storage flash memory. Excellent data retention capability is observed. This new flash memory uses no new high voltage device other than those already used for I/O and for normal programming and erase, and is completely compatible with normal fabrication processes.

Device modeling of ferroelectric memory field-effect transistor (FeMFET)

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.

An improved two-frequency method of capacitance measurement for SrTiO 3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO/sub 3/ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics.

A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (∼20 nm) and poly channel thickness (∼10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F∼2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, “Z-interference” in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.

A transient analysis method to characterize the trap vertical location in nitride-trapping devices

A new method to probe the trap vertical location for nitride-trapping devices is proposed. This method requires only measuring the time dependence of gate injection at various gate voltages on a single wafer. The transient current (J) and the instantaneous electric field (E) across the top oxide can be directly obtained based on various cases of trap location. Comparisons can be made to check which case has the best consistency for the J versus E behaviors. The only assumption in this method is that the transient current J and the instantaneous E field should follow a consistent tunneling relationship at different gate voltages. The experimental results show unequivocally that electrons are trapped at the interface between top oxide and nitride for oxide grown by thermal conversion. However, for the direct-deposited top oxide the electrons are more spatially distributed in the nitride. This method is a simple and convincing tool to detect the nitride trap vertical location.

A novel p-channel NAND-type flash memory with 2-bit/cell operation and high programming throughput (> 20 MB/sec)

A novel p-channel NAND-type non-volatile flash memory using nitride-trapping device is presented. The p-channel device is programmed by very efficient band-to-band tunneling hot electron (BBHE), and erased by self-converging channel hole tunneling. An ultra-thin bandgap engineered ONO tunneling dielectric as presented in H. T. Lue et al. (2005) is adopted to achieve efficient hole-tunneling erase at high electric field, but yet good data retention at low field. The operation of physically 2-bit/cell NAND-type architecture with depletion mode device (VT > 0) is illustrated. Excellent P/E cycling endurance, data retention and read disturb immunity are demonstrated. This new non-volatile p-channel memory device is capable of very high-programming throughput (> 20 MB/sec) suitable for data Flash application