Erh-Kun Lai

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

A low power phase change memory using thermally confined TaN/TiN bottom electrode

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

Understanding amorphous states of phase-change memory using Frenkel-Poole model

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

Mechanisms of retention loss in Ge 2 Sb 2 Te 5 -based Phase-Change Memory

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications

A novel Cycle Alarm Point (CAP) inspection is proposed to monitor PCM cycling degradation. The degradation appears in two stages - (1) right shift of R-I during moderate cycling degradation, and (2) left shift of R-I when cycling damage is severe. We further propose an In-Situ-Self-Anneal (ISSA) procedure, such that once a CAP signal is detected, the annealing procedure is issued to rejuvenate the cells. We demonstrate, for the first time, PCM cycling degradation can be recovered repeatedly. This opens a new window to extend PCM endurance and reliability for storage class memory (SCM) applications.

The impact of hole-induced electromigration on the cycling endurance of phase change memory

The high current density induced failure in Ge2Sb2Te5(GST)-based phase change memory (PCM) is investigated. A strong dependence of cycling endurance on the polarity of the operation current is observed and reported for the first time. The cycling endurance is reduced by 4 orders of magnitude when the current polarity is reversed. Careful TEM analysis of failed cells revealed a thin void in GST over the bottom electrode, but only in the reverse polarity samples. This phenomenon can be explained by hole-induced electromigration at the electrode/GST interface. The impact of electromigration on scaled phase change memory is discussed.

Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme

Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three independent 10X sensing windows (100KΩ~1MΩ × 3) all on same read speed. Each sensing window only needs to store 2~3 resistance levels instead of 8 levels needed in conventional MLC method, thus can tolerate resistance drift without closing the memory windows. A maximum of 16 levels of MLC is demonstrated on a 256Mb chip that is suitable for 4-bits/cell application.

Optimization of programming current on endurance of phase change memory

We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.

A thermally robust phase change memory by engineering the Ge/N concentration in (Ge, N) x Sb y Te z phase change material

Phase change memory (PCRAM) is an ideal embedded memory due to its simple BEOL process and low voltage operation. Industrial and automotive applications of PCRAM, however, have not been realized because of poor high temperature properties of the conventional Ge₂Sb₂Te₅ phase-change material [1-3]. We have previously reported a special Ge_xSb_yTe_z material along the Ge and Sb₂Te₃ tie line that showed superior high temperature performance. In this work we have further enhanced our previous “golden” material by incorporating nitrogen and engineering the Ge/N concentration. In order to rapidly explore a range of new materials a fast method to test retention behavior by laser melt-quenching is adopted which yields retention data on blanket films consistent with device results. A new material with special Ge/N concentration with excellent high temperature retention is discovered. The new material demonstrated nearly 100% yield in a 256 Mb test chip after 160 °C, 84 hrs baking, with projected 10-year retention at 120 °C. (> 9,000 years at 85 °C.).

A double-density dual-mode phase change memory using a novel background storage scheme

Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.