Patrick Jaenen

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).

Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

We present a number of compact wavelength-selective elements implemented in silicon-on-insulator (SOI) photonic wires. These include arrayed waveguide gratings (AWGs), Mach-Zehnder lattice filters (MZLFs), and ring resonators. The circuits were fabricated with deep UV lithography. We also address the sensitivity of photonic wires to phase noise by selectively broadening the waveguides, and demonstrate this in a compact AWG with -20 dB crosstalk and an insertion loss of 2.2 dB for the center channels

Fabrication of Photonic Wire and Crystal Circuits in Silicon-on-Insulator Using 193-nm Optical Lithography

High-index contrast silicon-on-insulator technology enables wavelength-scale compact photonic circuits. We report fabrication of photonic circuits in silicon-on-insulator using complementary metal-oxide-semiconductor processing technology. By switching from advanced optical lithography at 248 to 193 nm, combined with improved dry etching, a substantial improvement in process window, linearity, and proximity effect is achieved. With the developed fabrication process, propagation and bending loss of photonic wires were characterized. Measurements indicate a propagation loss of 2.7 dB/cm for 500-nm photonic wire and an excess bending loss of 0.013 dB/90deg bend of 5-mum radius. Through this paper, we demonstrate the suitability of high resolution optical lithography and dry etch processes for mass production of photonic integrated circuits.

Compact wavelength router based on a Silicon-on-insulator arrayed waveguide grating pigtailed to a fiber array

We demonstrate a compact, fiber-pigtailed, 4-by-4 wavelength router in Silicon-on-insulator photonic wires, fabricated using CMOS processing methods. The core is an AWG with a 250GHz channel spacing and 1THz free spectral range, on a 425x155 microm(2) footprint. The insertion loss of the AWG was reduced to 3.5dB by applying a two-step processing technique. The crosstalk is -12dB. The device was pigtailed using vertical fiber couplers and an eight-fiber array connector.

Linear and Nonlinear Nanophotonic Devices Based on Silicon-on-Insulator Wire Waveguides

We review the basic linear and nonlinear properties of silicon-on-insulator photonic wire waveguides and their application to nanophotonic circuits. We give an overview of the performance and issues of basic circuit elements such as couplers and intersections and review the achievements in linear wavelength-selective elements, as well as nonlinear applications of wires and resonators for high-speed signal processing.

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm ØTSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

In this study, we report on the processing and the electrical characterization of a 3D-WLP TSV flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn microbump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50µm. The actual TSV and microbump process uses 3 masks, two Si-DRIE steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35µm Ø TSV, 5µm thick polymer liner, 25µm Ø Cu, 50µm deep TSV, and a 60µm TSV pitch.