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Dive into the research topics where Kwang-Bok Kim is active.

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Featured researches published by Kwang-Bok Kim.


Japanese Journal of Applied Physics | 1998

Control of Microscratches in Chemical-Mechanical Polishing Process for Shallow Trench Isolation

Heungsoo Park; Kwang-Bok Kim; Chang-ki Hong; U-In Chung; Moonyong Lee

A method of controlling microscratches on silicon oxide surfaces induced by chemical-mechanical polishing (CMP) process for the planarization of shallow trench isolation is discussed. The frequency of microscratches during polishing shows its high dependency on the characteristics of CMP consumables such as slurry and pad. A diluted slurry solution, pH-controlled with a potassium hydroxide (KOH) solution of pH 13, produces best results in reducing microscratches on silicon oxide surfaces during polishing. In conclusion, careful preparation of the CMP consumables is required to reduce microscratches on silicon oxide during polishing.


MRS Proceedings | 1999

A Study of the Planarity by Sti Cmp Erosion Modeling

Kwang-Bok Kim; Sang-rok Hah; J.H. Han; C.K. Hong; U-In Chung; G.W. Kang

In this work, we propose a new equation that predicts the planarity as a function of active pattern density, initial step height, selectivity between gapfilled oxide and silicon nitride and over CMP amounts. In order to achieve highly planarized STI surface, uniform active density, reduced initial step height, minimization of over CMP amounts and high selective slurry were required. Our new equation was applied to the 0.18um graded CPU devices’ STI CMP to enhance planarity and these parameters were evaluated quantitatively. It is concluded that the model suggested is useful in predicting CMP planarity


MRS Proceedings | 2001

A Study on STI and Damascene CMP using Chip Level Simulation

Kyung-hyun Kim; Yoo-Hyon Kim; Kwang-Bok Kim; Chang-Ki Hong; Moon-Hyun Yoo

Simulation of chemical-mechanical polishing is important because the chip-level planarity are difficult to control. The simulator has been developed for predicting and optimizing the thickness distribution after the STI and damascene CMP as well as ILD CMP using chip-level pattern density, elastic spring model and erosion model. In this study, the results of CMP simulation is shown to agree well with the measured data. The simulator can be used to optimize CMP process conditions and to generate design rules for filling dummy patterns which are used to improve the planarity and uniformity.


Archive | 2003

Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same

Young-rae Park; Jung-yup Kim; Bo-Un Yoon; Kwang-Bok Kim; Jae-phill Boo; Jong-Won Lee; Sang-rok Hah; Kyung-hyun Kim; Chang-ki Hong


Archive | 2002

Method of planarizing non-volatile memory device

Min-Soo Cho; Dong-Jun Kim; Eui-Youl Ryu; Dai-Goun Kim; Young-Hee Kim; Sang-rok Hah; Kwang-Bok Kim; Jeong-Lim Nam; Kyung-hyun Kim


Archive | 2004

Method and system for planarizing integrated circuit material

Kwang-Bok Kim; Jae-Kwang Choi; Yong-Sun Ko; Chang-Ki Hong; Kyung-Hyun Kim; Jae-dong Lee


Archive | 2001

Method of fabricating a non-volatile memory device having a tunnel-insulating layer including more than two portions of different thickness

Jae-Phil Boo; Soo-Young Tak; Kwang-Bok Kim; Kyung-hyun Kim; Chang-ki Hong


Archive | 2005

Methods of fabricating trench type capacitors including protective layers for electrodes and capacitors so formed

Kwang-Bok Kim; Yong-Sun Ko; Kyung-Hyun Kim


Archive | 2009

Method of fabricating integrated circuit semiconductor device having gate metal silicide layer

Ki-ho Bae; Kwang-Bok Kim; Choongkee Seong; In-seak Hwang; Ki-Jong Park; Kyung-hyun Kim


Archive | 2016

BIOSENSOR ELECTRODE STRUCTURE AND BIOSENSOR INCLUDING THE SAME

Young-Jae Oh; Kwang-Bok Kim; Seong-Je Cho; Jae-Geol Cho; Hyoungseon Choi; Sun-tae Jung; Chul-Ho Cho

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