Kwang-Ho Ahn

An 880 / 1760 MHz tunable bandwidth active RC low-pass filter using high gain amplifier

For 60GHz unlicensed applications, an analog base-band filter using an active RC type is presented. An 880 / 1760 MHz tunable bandwidth third order Butterworth low-pass filter using high gain amplifiers is fabricated in 90nm standard CMOS process. Drawing 29.2 mW from 1.2 V power supply, the low frequency gains of the filter are -1.2 and -2.5 dB, and the output third order intercept points (OIP3) are +2.85 and +2.35 dBm for the single channel and channel bonding conditions, respectively.

Low Phase Noise Bond Wire VCO for DVB-H

A low phase noise VCO with the bond wire inductor for DVB-H is implemented in TSMC CMOS 0.18 mum process. The bond wire VCO exhibits -137 dBc/Hz @ 1MHz with the 5 mA current consumption. To meet the DVB-H phase noise requirement, bond wire modelling is introduced in this paper. Due to the bond wire characteristics, Q value of the VCO inductor is more than 25 at 1 GHz. The proposed bond wire inductor provides additional frequency tuning options after IC fabrication by modifying the length of the bond wire.

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

A background timing-mismatch calibration algorithm is proposed, which detects and corrects the sampling time mismatches in time-interleaved analog-to-digital converter (ADC) channels by analyzing the sign-equality of a reference slope and a timing-mismatch-induced error value. The sign of the ideal derivative along the input is estimated through the adjacent channel outputs, thus not requiring an additional time-shifted ADC channel. The sign of the reference slope, which is the estimated sign of the ideal derivative at the sampling edge of the reference ADC, is matched against the sign of the error value to determine if the timing mismatch is leading or lagging the sampling edge of the reference ADC. The proposed algorithm aligns the sampling edge of each subchannel to that of the reference ADC by handling only two sign bits and thus reduces the timing mismatches with only negligible hardware overhead consisting of simple logic gates.

Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs

A ternary-level thermometer capacitive digital-to-analog converter (C-DAC) switching scheme is proposed for flash-assisted successive-approximation register (FA-SAR) analog-to-digital converters (ADCs). By minimizing the capacitor reference switching operations of the C-DAC with the help of thermometer codes readily available from the assistant flash ADC, integral nonlinearity (INL) and differential nonlinearity (DNL), as well as C-DAC switching energy, are significantly improved from conventional switching schemes, which in turn makes near thermal-noise-limited capacitor designs feasible without complex capacitor weight calibrations.

mm-Wave CMOS Colpitts VCO & Frequency divider for the 60GHz WPAN

A mm-wave CMOS Colpitts VCO and Frequency divider for the 60GHz WPAN fabricated with the 90nm TSMC Process is presented. The VCO is composed of a NMOS transistor-pair as a core circuit and 3 bit capacitor array for enhancement of the oscillation bandwidth. A mm-wave frequency divider is designed based on CML divider driven by colpittss high voltage swing. The proposed VCO can operate at 28∼34GHz and the phase noise at 1MHz offset is −112dBc/Hz. The operating range of the suggested CML divider is 20∼46GHz when the driving voltage amplitude is 400mV. The power consumption of the VCO & divider including all the buffers is 30mW. Comparing to previous works, the proposed VCO & divider have the widest bandwidth at mm-wave frequency.

A design of tunable component for font end module

This paper describes VCO designs based on varactor tuned architecture. The oscillators of FMCW generator have been designed in a 0.13μm SiGe BiCMOS technology, thus targeting automotive Radar and millimeter-wave applications. Their tuning ranges are 2.98 GHz. The VCO chip achieve low phase noise characteristics -102.68 dBc/Hz at 1 MHz offset from the tunable frequency.

Ultra-Wideband CMOS Differential Colpitts VCO with adaptive gm bias for the 60GHz WPAN

A Ultra-Wideband CMOS Differential Colpitts VCO for 60GHz WPAN fabricated with the 90nm TSMC Process is presented. The VCO is composed of a NMOS transistor-pair as a core circuit, 3 bit capacitor array for enhancement of the oscillation bandwidth, and adaptive gm bias for desensitizing process variations. The proposed architecture can operate at 28∼34GHz and the phase noise at 1MHz offset is −112dBc/Hz. The power consumption of the VCO including inherent buffer is 21.6mW. Compared with previous studied works, the proposed VCO has the widest bandwidth at mm-Wave frequency.